programmerjake/cpu
1
0
Fork 0
forked from libre-chip/cpu
Code Pull requests Activity

ArrayVec::map: actually connect to all output elements

Browse source
This commit is contained in:
Jacob Lifshay 2026-05-29 01:31:29 -07:00
parent 9cecc6aaa0
commit 7fc205e583
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
crates/cpu/src/util/array_vec.rs
View file

@ -226,6 +226,10 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
#[hdl] #[hdl]
let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty)); let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
connect(mapped_array_vec.len, this.len); connect(mapped_array_vec.len, this.len);
connect(
mapped_array_vec.elements,
mapped_array_vec.ty().elements.uninit(),
);
Self::for_each(this, |index, element| { Self::for_each(this, |index, element| {
connect(mapped_array_vec[index], f(index, element)); connect(mapped_array_vec[index], f(index, element));
}); });