forked from libre-chip/cpu
WIP adding next_pc: added mock_fetch_decode_pipe
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6 changed files with 14654 additions and 4 deletions
340
crates/cpu/tests/next_pc.rs
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340
crates/cpu/tests/next_pc.rs
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@ -0,0 +1,340 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use cpu::{
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config::{CpuConfig, UnitConfig},
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next_pc::{
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DecodeToPostDecodeInterface, DecodeToPostDecodeInterfaceInner, FETCH_BLOCK_ID_WIDTH,
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NextPcToFetchInterface, NextPcToFetchInterfaceInner, WipDecodedInsn, WipDecodedInsnKind,
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next_pc,
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},
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unit::UnitKind,
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util::array_vec::ArrayVec,
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};
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use fayalite::{prelude::*, sim::vcd::VcdWriterDecls, util::RcWriter};
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use std::{
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cell::Cell,
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collections::{BTreeMap, VecDeque},
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num::NonZeroUsize,
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};
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#[derive(Copy, Clone, Debug)]
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enum MockInsn {
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Nop4,
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Jump { target: u64 },
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CondBranch { target: u64 },
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Call { target: u64 },
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Ret,
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}
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impl MockInsn {
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fn byte_len(self) -> u64 {
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match self {
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MockInsn::Nop4 => 4,
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MockInsn::Jump { .. } => 4,
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MockInsn::CondBranch { .. } => 4,
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MockInsn::Call { .. } => 4,
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MockInsn::Ret => 4,
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}
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}
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}
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#[derive(Debug)]
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struct MockInsns {
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insns: BTreeMap<u64, MockInsn>,
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}
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impl MockInsns {
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fn new() -> Self {
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Self {
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insns: BTreeMap::from_iter([
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(0x0, MockInsn::Nop4),
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(0x4, MockInsn::Nop4),
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(0x8, MockInsn::CondBranch { target: 0x4 }),
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(0xC, MockInsn::Call { target: 0x18 }),
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(0x10, MockInsn::Jump { target: 0x10 }),
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(0x14, MockInsn::Jump { target: 0x10 }),
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(0x18, MockInsn::Jump { target: 0x1C }),
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(0x1C, MockInsn::Ret),
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]),
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}
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}
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fn fetch_block(&self, pc_range: std::ops::Range<u64>) -> impl Iterator<Item = (u64, MockInsn)> {
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self.insns
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.range(pc_range.clone())
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.filter_map(move |(&pc, &insn)| {
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if pc_range.end >= pc + insn.byte_len() {
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Some((pc, insn))
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} else {
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None
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}
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})
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}
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}
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const FETCH_PIPE_QUEUE_SIZE: usize = 5;
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const DEMO_ILLEGAL_INSN_TRAP: u64 = 0xFF000000u64;
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#[hdl]
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struct FetchPipeQueueEntry {
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fetch_pc: UInt<64>,
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cycles_left: UInt<8>,
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fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>,
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}
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impl FetchPipeQueueEntry {
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#[hdl]
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fn default_sim(self) -> SimValue<Self> {
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#[hdl(sim)]
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FetchPipeQueueEntry {
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fetch_pc: 0u64,
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cycles_left: 0u8,
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fetch_block_id: 0u8,
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}
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}
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fn get_next_delay(delay_sequence_index: &Cell<u64>) -> u8 {
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let index = delay_sequence_index.get();
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delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1));
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// make a pseudo-random number deterministically based on index
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let random = index
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.wrapping_add(1)
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.wrapping_mul(0x18C49126EABE7A0D) // random prime
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.rotate_left(32)
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.wrapping_mul(0x92B38C197608A6B) // random prime
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.rotate_right(60);
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(random % 8) as u8
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}
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}
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#[hdl_module(extern)]
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fn mock_fetch_pipe(config: PhantomConst<CpuConfig>) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let from_fetch: NextPcToFetchInterface<PhantomConst<CpuConfig>> =
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m.input(NextPcToFetchInterface[config]);
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#[hdl]
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let to_post_decode: DecodeToPostDecodeInterface<PhantomConst<CpuConfig>> =
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m.output(DecodeToPostDecodeInterface[config]);
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#[hdl]
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let queue_debug: ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>> =
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m.output();
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m.register_clock_for_past(cd.clk);
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m.extern_module_simulation_fn(
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(cd, from_fetch, to_post_decode, queue_debug),
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|(cd, from_fetch, to_post_decode, queue_debug), mut sim| async move {
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// intentionally have a different sequence each time we're reset
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let delay_sequence_index = Cell::new(0);
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sim.resettable(
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cd,
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async |mut sim| {
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sim.write(from_fetch.inner.ready, false).await;
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sim.write(
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to_post_decode.inner.data,
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to_post_decode.ty().inner.data.HdlNone(),
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)
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.await;
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sim.write(
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queue_debug,
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queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim()),
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)
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.await;
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},
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|sim, ()| {
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run_fn(
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cd,
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from_fetch,
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to_post_decode,
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queue_debug,
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&delay_sequence_index,
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sim,
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)
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},
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)
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.await;
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},
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);
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#[hdl]
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async fn run_fn(
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cd: Expr<ClockDomain>,
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from_fetch: Expr<NextPcToFetchInterface<PhantomConst<CpuConfig>>>,
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to_post_decode: Expr<DecodeToPostDecodeInterface<PhantomConst<CpuConfig>>>,
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queue_debug: Expr<ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>>>,
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delay_sequence_index: &Cell<u64>,
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mut sim: ExternModuleSimulationState,
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) {
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let config = from_fetch.config.ty();
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let mock_insns = MockInsns::new();
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let mut queue: VecDeque<SimValue<FetchPipeQueueEntry>> = VecDeque::new();
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let mut next_id = 0u32;
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loop {
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let mut sim_queue = queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim());
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for entry in &queue {
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ArrayVec::try_push_sim(&mut sim_queue, entry)
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.ok()
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.expect("queue is known to be small enough");
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}
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sim.write(queue_debug, sim_queue).await;
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if let Some(front) = queue.front().filter(|v| v.cycles_left.as_int() == 0) {
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#[hdl(sim)]
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let FetchPipeQueueEntry {
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fetch_pc,
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cycles_left: _,
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fetch_block_id,
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} = front;
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let fetch_pc = fetch_pc.as_int();
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let fetch_end =
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(fetch_pc + 1).next_multiple_of(config.get().fetch_width_in_bytes() as u64);
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let insns = to_post_decode.ty().inner.data.HdlSome.insns;
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let zeroed_insn = UInt[insns.element().canonical().bit_width()]
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.zero()
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.cast_bits_to(insns.element());
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let mut insns = insns.new_sim(zeroed_insn);
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let mut expected_pc = fetch_pc;
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// TODO: handle instructions that go past the end of a fetch block
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for (pc, insn) in mock_insns.fetch_block(fetch_pc..fetch_end) {
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let next_pc = pc + insn.byte_len();
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if pc != expected_pc {
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break;
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}
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expected_pc = next_pc;
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let kind = match insn {
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MockInsn::Nop4 => WipDecodedInsnKind.NonBranch(),
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MockInsn::Jump { target } => WipDecodedInsnKind.Branch(target),
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MockInsn::CondBranch { target } => WipDecodedInsnKind.BranchCond(target),
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MockInsn::Call { target } => WipDecodedInsnKind.Call(target),
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MockInsn::Ret => WipDecodedInsnKind.Ret(),
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};
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let insn = #[hdl(sim)]
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WipDecodedInsn {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc,
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size_in_bytes: insn.byte_len().cast_to_static::<UInt<_>>(),
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kind,
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};
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match ArrayVec::try_push_sim(&mut insns, insn) {
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Ok(()) => next_id = next_id.wrapping_add(1),
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Err(_) => break,
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}
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}
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if **ArrayVec::len_sim(&insns) == 0 {
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let Ok(()) = ArrayVec::try_push_sim(
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&mut insns,
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#[hdl(sim)]
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WipDecodedInsn {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc: fetch_pc,
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size_in_bytes: 0u8.cast_to_static::<UInt<_>>(),
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kind: WipDecodedInsnKind.Interrupt(DEMO_ILLEGAL_INSN_TRAP),
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},
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) else {
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unreachable!();
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};
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next_id = next_id.wrapping_add(1);
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}
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sim.write(
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to_post_decode.inner.data,
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HdlSome(
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#[hdl(sim)]
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DecodeToPostDecodeInterfaceInner::<_> { insns, config },
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),
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)
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.await;
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} else {
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sim.write(
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to_post_decode.inner.data,
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to_post_decode.ty().inner.data.HdlNone(),
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)
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.await;
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}
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sim.write(from_fetch.inner.ready, queue.len() < FETCH_PIPE_QUEUE_SIZE)
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.await;
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sim.wait_for_clock_edge(cd.clk).await;
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if sim.read_past_bool(to_post_decode.inner.ready, cd.clk).await {
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#[hdl(sim)]
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if let HdlSome(_) = sim.read_past(to_post_decode.inner.data, cd.clk).await {
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queue.pop_front();
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}
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}
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for entry in &mut queue {
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if entry.cycles_left.as_int() > 0 {
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entry.cycles_left = (entry.cycles_left.as_int() - 1u8).to_sim_value();
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}
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}
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if !sim.read_past_bool(from_fetch.inner.ready, cd.clk).await {
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continue;
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}
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#[hdl(sim)]
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if let HdlSome(inner) = sim.read_past(from_fetch.inner.data, cd.clk).await {
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#[hdl(sim)]
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let NextPcToFetchInterfaceInner {
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next_fetch_pc,
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fetch_block_id,
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in_progress_fetches_to_cancel,
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} = &inner;
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// cancel in-progress fetches from newest to oldest
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for _ in 0..in_progress_fetches_to_cancel.as_int() {
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let _ = queue.pop_back();
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}
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queue.push_back(
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#[hdl(sim)]
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FetchPipeQueueEntry {
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fetch_pc: next_fetch_pc,
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cycles_left: FetchPipeQueueEntry::get_next_delay(delay_sequence_index),
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fetch_block_id,
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},
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);
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}
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}
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}
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}
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#[hdl_module]
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fn dut(config: PhantomConst<CpuConfig>) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let next_pc = instance(next_pc(config));
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connect(next_pc.cd, cd);
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#[hdl]
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let mock_fetch_pipe = instance(mock_fetch_pipe(config));
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connect(mock_fetch_pipe.cd, cd);
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connect(mock_fetch_pipe.from_fetch, next_pc.to_fetch);
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connect(next_pc.from_decode, mock_fetch_pipe.to_post_decode);
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}
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#[hdl]
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#[test]
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fn test_next_pc() {
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let _n = SourceLocation::normalize_files_for_tests();
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let mut config = CpuConfig::new(
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vec![
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UnitConfig::new(UnitKind::AluBranch),
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UnitConfig::new(UnitKind::AluBranch),
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],
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NonZeroUsize::new(20).unwrap(),
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);
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config.fetch_width = NonZeroUsize::new(2).unwrap();
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let m = dut(PhantomConst::new_sized(config));
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let mut sim = Simulation::new(m);
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let mut writer = RcWriter::default();
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sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
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sim.write_clock(sim.io().cd.clk, false);
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sim.write_reset(sim.io().cd.rst, true);
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for _cycle in 0..300 {
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sim.advance_time(SimDuration::from_nanos(500));
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sim.write_clock(sim.io().cd.clk, true);
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sim.advance_time(SimDuration::from_nanos(500));
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sim.write_clock(sim.io().cd.clk, false);
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sim.write_reset(sim.io().cd.rst, false);
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}
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// FIXME: vcd is just whatever next_pc does now, which isn't known to be correct
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let vcd = String::from_utf8(writer.take()).unwrap();
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println!("####### VCD:\n{vcd}\n#######");
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if vcd != include_str!("expected/next_pc.vcd") {
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panic!();
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}
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}
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