From 67e9f598f769b64ffc6f655836db837b96f1b593 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 10 Jul 2026 19:16:13 -0700 Subject: [PATCH] WIP: adding load/store unit --- .cargo/config.toml | 4 + crates/cpu/src/instruction.rs | 14 + crates/cpu/src/main_memory_and_io.rs | 39 + crates/cpu/src/unit.rs | 5 +- crates/cpu/src/unit/alu_branch.rs | 1 + crates/cpu/src/unit/load_store.rs | 1330 +++ .../tests/expected/load_store_unit_random.vcd | 9163 +++++++++++++++++ crates/cpu/tests/load_store_unit.rs | 1960 ++++ crates/cpu/tests/units_formal.rs | 8 +- 9 files changed, 12521 insertions(+), 3 deletions(-) create mode 100644 .cargo/config.toml create mode 100644 crates/cpu/src/unit/load_store.rs create mode 100644 crates/cpu/tests/expected/load_store_unit_random.vcd create mode 100644 crates/cpu/tests/load_store_unit.rs diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..61e31ad --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information +[build] +rustflags = ["-Csymbol-mangling-version=v0", "-Cforce-frame-pointers=yes"] \ No newline at end of file diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index 336da53..bf4be7b 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -19,6 +19,7 @@ use std::{ borrow::Cow, fmt, marker::PhantomData, + num::NonZeroU64, ops::{ControlFlow, Range}, }; @@ -2983,6 +2984,19 @@ pub enum LoadStoreWidth { Width64Bit, } +impl LoadStoreWidth { + #[hdl] + pub fn access_byte_size_sim(this: &::SimValue) -> NonZeroU64 { + #[hdl(sim)] + match this { + Self::Width8Bit => const { NonZeroU64::new(1).unwrap() }, + Self::Width16Bit => const { NonZeroU64::new(2).unwrap() }, + Self::Width32Bit => const { NonZeroU64::new(4).unwrap() }, + Self::Width64Bit => const { NonZeroU64::new(8).unwrap() }, + } + } +} + #[hdl(cmp_eq)] pub enum LoadStoreConversion { ZeroExt, diff --git a/crates/cpu/src/main_memory_and_io.rs b/crates/cpu/src/main_memory_and_io.rs index 5a1a853..795bf84 100644 --- a/crates/cpu/src/main_memory_and_io.rs +++ b/crates/cpu/src/main_memory_and_io.rs @@ -127,8 +127,47 @@ impl AddressRange { }, } } + pub const fn is_overlapping(self, other: Self) -> bool { + self.contains(other.start().0) || other.contains(self.start().0) + } } +const _: () = { + const N: u64 = 4; + const fn is_overlapping_reference(range1: AddressRange, range2: AddressRange) -> bool { + // we just need to check values < N since all starts/ends are < N + let mut v = 0; + while v < N { + if range1.contains(v) && range2.contains(v) { + return true; + } + v += 1; + } + false + } + let mut start1 = 0; + while start1 < N { + let mut end1 = 0; + while end1 < N { + let mut start2 = 0; + while start2 < N { + let mut end2 = 0; + while end2 < N { + let range1 = AddressRange::from_wrapping_range_inclusive(start1..=end1); + let range2 = AddressRange::from_wrapping_range_inclusive(start2..=end2); + assert!( + range1.is_overlapping(range2) == is_overlapping_reference(range1, range2) + ); + end2 += 1; + } + start2 += 1; + } + end1 += 1; + } + start1 += 1; + } +}; + #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, serde::Serialize, serde::Deserialize)] #[non_exhaustive] pub struct MemoryInterfaceConfig { diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index d7442a3..4864125 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -8,6 +8,7 @@ use crate::{ MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, mop_enum, }, rename_execute_retire::ExecuteToUnitInterface, + unit::load_store::LoadStoreToDCacheInterface, }; use fayalite::{ bundle::{Bundle, BundleType}, @@ -18,6 +19,7 @@ use serde::{Deserialize, Serialize}; use std::ops::ControlFlow; pub mod alu_branch; +pub mod load_store; macro_rules! all_units { ( @@ -333,7 +335,7 @@ all_units! { #[create_dyn_unit_fn = |config, unit_index, filter| todo!()] #[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)] TransformedMove(TransformedMoveOp), - #[create_dyn_unit_fn = |config, unit_index, filter| todo!()] + #[create_dyn_unit_fn = |config, unit_index, filter| load_store::LoadStore::new(config, unit_index, filter).to_dyn()] #[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)] LoadStore(LoadStoreMOp), } @@ -391,6 +393,7 @@ impl RenamedMOpFilter for () { pub struct UnitIO { pub cd: Option>, pub from_execute: Expr>>, + pub to_d_cache: Option>>>, } pub trait UnitTrait: diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index 52bd4ab..4af688a 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -1617,6 +1617,7 @@ impl UnitTrait for AluBranch { UnitIO { cd: None, from_execute: this.from_execute, + to_d_cache: None, } } diff --git a/crates/cpu/src/unit/load_store.rs b/crates/cpu/src/unit/load_store.rs new file mode 100644 index 0000000..77b16da --- /dev/null +++ b/crates/cpu/src/unit/load_store.rs @@ -0,0 +1,1330 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::{CpuConfig, PhantomConstCpuConfig}, + instruction::{ + COMMON_MOP_SRC_LEN, LoadMOp, LoadStoreCommonMOp, LoadStoreConversion, LoadStoreMOp, + LoadStoreWidth, PRegNum, StoreMOp, + }, + main_memory_and_io::{AddressRange, MemoryOperationErrorKind}, + next_pc::{CallStackOp, SimValueDefault}, + register::{PRegFlags, PRegValue}, + rename_execute_retire::{ + ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp, UnitEnqueue, + UnitFinishCauseCancel, UnitInputsReady, UnitMOpCantCauseCancel, + UnitMOpIsNoLongerSpeculative, UnitOutputReady, + }, + unit::{DynUnit, DynUnitWrapper, RenamedMOpFilter, UnitIO, UnitKind, UnitMOp, UnitTrait}, +}; +use fayalite::{intern::Interned, prelude::*, ty::SimValueDebug, util::ready_valid::ReadyValid}; +use std::{collections::VecDeque, fmt}; + +pub const MAX_LOAD_STORE_SIZE: usize = 8; + +#[hdl] +pub struct DCacheOpKindLoad { + /// if this is `false`, then if the address refers to a valid cache line, that cache line must have any dirty data + /// written back to memory and then be set to invalid before performing the load. + pub is_cacheable: Bool, +} + +#[hdl] +pub struct DCacheOpKindStore { + /// if this is `false`, then if the address refers to a valid cache line, that cache line must have any dirty data + /// written back to memory and then be set to invalid before performing the store. + pub is_cacheable: Bool, +} + +#[hdl] +pub enum DCacheOpKind { + Load(DCacheOpKindLoad), + Store(DCacheOpKindStore), +} + +#[hdl] +pub struct DCacheStart> { + pub id: MOpId, + pub kind: DCacheOpKind, + /// unaligned addresses may cause a load/store to cross a cache-line boundary + pub address: UInt<64>, + pub data_and_mask: Array>, { MAX_LOAD_STORE_SIZE }>, + pub config: C, +} + +#[hdl] +pub enum DCacheFinishStatus { + /// The operation finished successfully + Success, + MemoryError(MemoryOperationErrorKind), +} + +#[hdl] +pub struct DCacheFinish> { + pub id: MOpId, + pub status: DCacheFinishStatus, + pub data: Array, { MAX_LOAD_STORE_SIZE }>, + pub config: C, +} + +/// This load must only look in the L1 cache (must not propagate to the L2/L3 cache or to memory), must not +/// cause the timing of any earlier speculative operations or any non-speculative operations to change +/// because this load exists, and must not change any cache state that remains after all operations finish, +/// including LRU state, random number generators, predictive prefetching state, etc. +/// +/// Speculative loads that miss the L1 cache must return with [`DCacheFinishSpeculativeLoad::data`] set to +/// [`HdlNone()`] instead of trying to propagate to the L2/L3 or memory. +#[hdl] +pub struct DCacheStartSpeculativeLoad> { + pub id: MOpId, + /// unaligned addresses may cause a load to cross a cache-line boundary + pub address: UInt<64>, + pub mask: Array, + pub config: C, +} + +#[hdl] +pub struct DCacheFinishSpeculativeLoad> { + pub id: MOpId, + pub data: HdlOption, { MAX_LOAD_STORE_SIZE }>>, + pub config: C, +} + +/// This CPU core's D-cache must report to the [load/store unit](load_store()) whenever: +/// * A cache line is removed from the D-cache by this CPU core (e.g. the cache ran out of space or the +/// cache line was intentionally removed by some instruction). +/// * Or a cache line is removed and/or written by something other than this CPU core (so other cores +/// and I/O devices that write to memory). +/// +/// That allows the [load/store unit](load_store()) to restart speculative loads as necessary to +/// maintain sequential consistency. +#[hdl] +pub struct DCacheForeignWriteToCacheLine> { + /// The address of the cache line that was written. + pub cache_line_address: UInt<64>, + /// Must be set such that for all bytes that were written and/or removed from the D-cache, that + /// `cache_line_address` must equal `cache_line_address_mask & byte_address`. + /// + /// e.g. if a 64-byte cache line at `0x1000` was removed, then `cache_line_address` is `0x1000` + /// and `cache_line_address_mask` is `0xFFFF_FFFF_FFFF_FFC0`. + pub cache_line_address_mask: UInt<64>, + pub config: C, +} + +#[hdl] +pub struct LoadStoreToDCacheInterface> { + /// Operations started through `start` must maintain sequential consistency -- so earlier operations + /// can't appear to have happened after later operations. + pub start: ReadyValid>, + /// operations must finish in the same order they started. + #[hdl(flip)] + pub finish: ReadyValid>, + /// It's valid for `start_speculative_load.ready` to be `false` at any time (or even always) + /// -- this doesn't block forward progress since speculative loads that don't start will eventually + /// convert to non-speculative loads and go through `start` instead. + /// + /// Speculative loads don't need to maintain any order relative to non-speculative operations, except + /// that speculative loads started after non-speculative operations have finished must be ordered after + /// those non-speculative operations (that should be trivial to implement in the D-cache). + /// + /// The [load/store unit](load_store()) will handle restarting speculative loads as necessary to + /// maintain sequential consistency when there is a `foreign_write_to_cache_line` that conflicts with + /// that load. + pub start_speculative_load: ReadyValid>, + /// Operations must finish in the same order they started. + #[hdl(flip)] + pub finish_speculative_load: ReadyValid>, + #[hdl(flip)] + pub foreign_write_to_cache_line: HdlOption>, + pub config: C, +} + +#[hdl(custom_debug(sim))] +struct OpDebugState { + v: SimOnly, +} + +impl SimValueDebug for OpDebugState { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + f.write_str(&value.v) + } +} + +impl SimValueDefault for OpDebugState { + #[hdl] + fn sim_value_default(self) -> SimValue { + thread_local! { + static VALUE: SimOnlyValue = SimOnlyValue::new("None".into()); + } + VALUE.with(|v| { + #[hdl(sim)] + Self { v } + }) + } +} + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +enum OpState { + InputNotReady, + StartedSpeculativeLoad, + FinishedSpeculativeLoad, + StartedLoadStore, + FinishedLoadStore, +} + +impl OpState { + fn as_str(self) -> &'static str { + match self { + Self::InputNotReady => "inr", + Self::StartedSpeculativeLoad => "ssl", + Self::FinishedSpeculativeLoad => "fsl", + Self::StartedLoadStore => "sls", + Self::FinishedLoadStore => "fls", + } + } +} + +impl fmt::Display for OpState { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.write_str(self.as_str()) + } +} + +#[derive(Debug)] +struct Op { + id: SimValue, + pc: SimValue>, + size_in_bytes: u8, + mop: SimValue, PRegNum>>, + /// earlier instructions can cause a cancel, so this instruction is still speculative. + /// not to be confused with this instruction being able to cause a cancel. + is_speculative: bool, + src_values: Option<[SimValue>; COMMON_MOP_SRC_LEN]>, + dest_value: Option>>, + sent_cant_cause_cancel: bool, + sent_output_ready: bool, + state: OpState, +} + +impl fmt::Display for Op { + #[hdl] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + id, + pc, + size_in_bytes, + mop, + is_speculative, + src_values, + dest_value, + sent_cant_cause_cancel, + sent_output_ready, + state, + } = self; + if *is_speculative { + f.write_str("(s)")?; + } + if *sent_cant_cause_cancel { + f.write_str("(sccc)")?; + } + if *sent_output_ready { + f.write_str("(sor)")?; + } + write!( + f, + "({state}) id={id:?} pc={pc:?} sz={size_in_bytes}: {mop:?}" + )?; + if let Some(src_values) = src_values { + write!(f, "src_values={src_values:?}")?; + } + if let Some(dest_value) = dest_value { + write!(f, "dest_value={dest_value:?}")?; + } + Ok(()) + } +} + +struct AccessRangeUnknown; + +impl Op { + fn new( + id: SimValue, + pc: SimValue>, + size_in_bytes: u8, + mop: SimValue, PRegNum>>, + ) -> Self { + Self { + id, + pc, + size_in_bytes, + mop, + is_speculative: true, + src_values: None, + dest_value: None, + sent_cant_cause_cancel: false, + sent_output_ready: false, + state: OpState::InputNotReady, + } + } + #[hdl] + fn debug_state(&self) -> SimValue { + #[hdl(sim)] + OpDebugState { + v: SimOnlyValue::new(self.to_string()), + } + } + #[hdl] + fn access_range_helper( + &self, + load_store_common: &SimValue, PRegNum, SrcCount>>, + ) -> Result { + let Some([src0, ..]) = &self.src_values else { + return Err(AccessRangeUnknown); + }; + let size = LoadStoreWidth::access_byte_size_sim(&load_store_common.width); + Ok(AddressRange::Limited { + start: std::num::Wrapping(src0.inner().int_fp.as_int()), + size, + }) + } + #[hdl] + fn access_range(&self) -> Result { + #[hdl(sim)] + match &self.mop { + LoadStoreMOp::<_, _>::Load(mop) => self.access_range_helper(&mop.load_store_common), + LoadStoreMOp::<_, _>::Store(mop) => self.access_range_helper(&mop.load_store_common), + } + } + fn can_cause_cancel(&self) -> bool { + if self.is_speculative { + return true; + } + match self.state { + OpState::InputNotReady + | OpState::StartedSpeculativeLoad + | OpState::StartedLoadStore => true, + OpState::FinishedSpeculativeLoad | OpState::FinishedLoadStore => { + self.dest_value.is_none() + } + } + } +} + +#[hdl(get(|c| c.rob_size.get().next_power_of_two()))] +type OpsDebugLen> = DynSize; + +#[hdl] +type PhantomConstUnitIndex = PhantomConst; + +#[hdl(no_static)] +pub struct LoadStoreDebugState> { + global_state: GlobalState, + ops: ArrayType, OpsDebugLen>, + canceling: Bool, + config: C, + unit_index: PhantomConstUnitIndex, + filter: LoadStoreFilter, +} + +#[derive(Debug)] +struct LoadStoreState { + global_state: SimValue, + ops: VecDeque>, + d_cache_start: Option>>, + d_cache_start_speculative_load: Option>>, + canceling: bool, + config: C, + unit_index: usize, + filter: SimValue, +} + +impl LoadStoreState { + fn new(config: C, unit_index: usize, filter: SimValue) -> Self { + Self { + global_state: GlobalState.sim_value_default(), + ops: VecDeque::new(), + d_cache_start: None, + d_cache_start_speculative_load: None, + canceling: false, + config, + unit_index, + filter, + } + } + #[hdl] + fn debug_state(&self) -> SimValue> { + let Self { + ref global_state, + ops: _, + // not included in debug state since it's identical to `to_d_cache.start.data` + d_cache_start: _, + // not included in debug state since it's identical to `to_d_cache.start_speculative_load.data` + d_cache_start_speculative_load: _, + canceling, + config, + unit_index, + ref filter, + } = *self; + let ty = LoadStoreDebugState[config]; + let mut ops = vec![OpDebugState.sim_value_default().into_trace_as_string(); ty.ops.len()]; + for op in &self.ops { + ops[op.id.as_int() as usize % ty.ops.len()] = op.debug_state().into_trace_as_string(); + } + #[hdl(sim)] + LoadStoreDebugState::<_> { + global_state, + ops, + canceling, + config, + unit_index: PhantomConst::new_sized(unit_index), + filter, + } + } + #[track_caller] + fn op_by_id(&mut self, id: &::SimValue) -> &mut Op { + match self.ops.iter_mut().find(|op| *op.id == *id) { + Some(op) => op, + None => panic!("can't find load_store Op with id {id:?}"), + } + } + fn from_execute_enqueue_ready(&self) -> bool { + !self.canceling + && self.ops.len() < self.config.get().unit_max_in_flight(self.unit_index).get() + } + #[hdl] + fn from_execute_enqueue(&mut self, enqueue: SimValue>) { + #[hdl(sim)] + let UnitEnqueue::<_> { mop, config: _ } = enqueue; + #[hdl(sim)] + let MOpInstance::<_> { + fetch_block_id: _, + id, + pc, + predicted_next_pc: _, + size_in_bytes, + is_first_mop_in_insn: _, + is_last_mop_in_insn: _, + mop, + } = mop; + let mop = #[hdl(sim)] + match SimValue::into_value(mop).into_inner() { + UnitMOp::<_, _, _>::LoadStore(mop) => mop, + _ => unreachable!(), + }; + self.ops.push_back(Op::new( + id, + pc, + size_in_bytes.cast_to_static::>().as_int(), + mop, + )); + } + #[hdl] + fn from_execute_inputs_ready(&mut self, inputs_ready: SimValue>) { + #[hdl(sim)] + let UnitInputsReady::<_> { + mop, + src_values, + config: _, + } = inputs_ready; + self.op_by_id(&mop.id).src_values = Some(SimValue::into_value(src_values)); + } + #[hdl] + fn from_execute_is_no_longer_speculative( + &mut self, + is_no_longer_speculative: SimValue>, + ) { + #[hdl(sim)] + let UnitMOpIsNoLongerSpeculative::<_> { id, config: _ } = is_no_longer_speculative; + self.op_by_id(&id).is_speculative = false; + } + #[hdl] + fn from_execute_cant_cause_cancel(&self) -> Option>> { + if self.canceling { + return None; + } + for op in &self.ops { + if op.sent_cant_cause_cancel || op.can_cause_cancel() { + continue; + } + return Some( + #[hdl(sim)] + UnitMOpCantCauseCancel::<_> { + id: op.id, + config: self.config, + }, + ); + } + None + } + #[hdl] + fn from_execute_sent_cant_cause_cancel( + &mut self, + cant_cause_cancel: SimValue>, + ) { + #[hdl(sim)] + let UnitMOpCantCauseCancel::<_> { id, config: _ } = cant_cause_cancel; + self.op_by_id(&id).sent_cant_cause_cancel = true; + } + #[hdl] + fn from_execute_output_ready(&self) -> Option>> { + if self.canceling { + return None; + } + for op in &self.ops { + if op.sent_output_ready { + continue; + } + if let Some(dest_value) = &op.dest_value { + return Some( + #[hdl(sim)] + UnitOutputReady::<_> { + id: op.id, + dest_value, + predictor_op: #[hdl(sim)] + NextPcPredictorOp::<_> { + call_stack_op: #[hdl(sim)] + CallStackOp.None(), + cond_br_taken: #[hdl(sim)] + HdlNone(), + config: self.config, + }, + }, + ); + } + } + None + } + #[hdl] + fn from_execute_sent_output_ready(&mut self, output_ready: SimValue>) { + #[hdl(sim)] + let UnitOutputReady::<_> { + id, + dest_value: _, + predictor_op: _, + } = output_ready; + self.op_by_id(&id).sent_output_ready = true; + } + #[hdl] + fn from_execute_finish_cause_cancel(&self) -> Option>> { + if self.canceling { + return None; + } + let Op { + id, + pc: _, + size_in_bytes: _, + mop: _, + is_speculative, + src_values: _, + dest_value, + sent_cant_cause_cancel: _, + sent_output_ready, + state, + } = self.ops.front()?; + if *is_speculative { + return None; + } + let retval_ty = UnitFinishCauseCancel[self.config]; + match state { + OpState::InputNotReady => None, + OpState::StartedSpeculativeLoad => None, + OpState::FinishedSpeculativeLoad => { + if *sent_output_ready { + // TODO: handle when some other CPU stores to the same cache line before the speculative + // load sends UnitFinishCauseCancel -- that needs to make the load cause a cancel so it + // can be redone with the correct data. That enforces sequential consistency. + Some( + #[hdl(sim)] + UnitFinishCauseCancel::<_> { + id, + caused_cancel: #[hdl(sim)] + (retval_ty.caused_cancel).HdlNone(), + config: self.config, + }, + ) + } else { + None + } + } + OpState::StartedLoadStore => None, + OpState::FinishedLoadStore => { + if dest_value.is_none() { + todo!("load/store caused error -- need to translate to a cancel"); + } + if *sent_output_ready { + Some( + #[hdl(sim)] + UnitFinishCauseCancel::<_> { + id, + caused_cancel: #[hdl(sim)] + (retval_ty.caused_cancel).HdlNone(), + config: self.config, + }, + ) + } else { + None + } + } + } + } + #[hdl] + fn from_execute_sent_finish_cause_cancel( + &mut self, + finish_cause_cancel: SimValue>, + ) { + let op = self + .ops + .pop_front_if(|front| front.id == finish_cause_cancel.id); + assert!( + op.is_some(), + "inconsistent state -- sent finish_cause_cancel but id doesn't match ops.front():\n{finish_cause_cancel:#?}\nfront={front:#?}", + front = self.ops.front(), + ); + } + fn from_execute_cancel_all_ready(&self) -> bool { + true + } + #[hdl] + fn from_execute_cancel_all(&mut self) { + self.canceling = true; + } + #[hdl] + fn to_d_cache_sent_start(&mut self, start: SimValue>) { + self.op_by_id(&start.id).state = OpState::StartedLoadStore; + } + #[hdl] + fn to_d_cache_finish_ready(&self) -> bool { + true + } + #[hdl] + fn to_d_cache_finish(&mut self, finish: SimValue>) { + #[hdl(sim)] + let DCacheFinish::<_> { + id, + status, + data, + config: _, + } = finish; + let canceling = self.canceling; + let op = self.op_by_id(&id); + op.state = OpState::FinishedLoadStore; + if canceling { + return; + } + #[hdl(sim)] + match status { + DCacheFinishStatus::Success => { + op.dest_value = #[hdl(sim)] + match &op.mop { + LoadStoreMOp::<_, _>::Load(mop) => Some(Self::process_load_data( + mop, + &SimValue::into_value(data).map(|v| v.as_int()), + )), + LoadStoreMOp::<_, _>::Store(_) => { + Some(PRegValue::zeroed_sim().into_trace_as_string()) + } + }; + } + DCacheFinishStatus::MemoryError(error) => { + todo!("{error:?}") + } + } + } + #[hdl] + fn to_d_cache_sent_start_speculative_load( + &mut self, + start_speculative_load: SimValue>, + ) { + self.op_by_id(&start_speculative_load.id).state = OpState::StartedSpeculativeLoad; + } + #[hdl] + fn to_d_cache_finish_speculative_load_ready(&self) -> bool { + true + } + #[hdl] + fn to_d_cache_finish_speculative_load( + &mut self, + finish_speculative_load: SimValue>, + ) { + #[hdl(sim)] + let DCacheFinishSpeculativeLoad::<_> { + id, + data, + config: _, + } = finish_speculative_load; + let canceling = self.canceling; + let op = self.op_by_id(&id); + op.state = OpState::FinishedSpeculativeLoad; + if canceling { + return; + } + #[hdl(sim)] + if let HdlSome(data) = data { + op.dest_value = #[hdl(sim)] + match &op.mop { + LoadStoreMOp::<_, _>::Load(mop) => Some(Self::process_load_data( + mop, + &SimValue::into_value(data).map(|v| v.as_int()), + )), + LoadStoreMOp::<_, _>::Store(_) => { + unreachable!() + } + }; + } + } + #[hdl] + fn to_d_cache_foreign_write_to_cache_line( + &mut self, + foreign_write_to_cache_line: SimValue>, + ) { + #[hdl(sim)] + let DCacheForeignWriteToCacheLine::<_> { + cache_line_address, + cache_line_address_mask, + config: _, + } = foreign_write_to_cache_line; + todo!( + "foreign_write_to_cache_line:\n\ + cache_line_address={cache_line_address}, cache_line_address_mask={cache_line_address_mask}" + ); + } + #[hdl] + fn canceling_step(&mut self) { + self.d_cache_start = None; + self.d_cache_start_speculative_load = None; + let finished_canceling = |op: &mut Op<_>| match op.state { + OpState::InputNotReady => true, + OpState::StartedSpeculativeLoad => false, + OpState::FinishedSpeculativeLoad => true, + OpState::StartedLoadStore => false, + OpState::FinishedLoadStore => true, + }; + while let Some(_) = self.ops.pop_front_if(finished_canceling) {} + if self.ops.is_empty() { + self.canceling = false; + } + } + fn is_cacheable_load(mop: &SimValue, PRegNum>>) -> bool { + // TODO: implement un-cacheable loads + true + } + fn is_cacheable_store(mop: &SimValue, PRegNum>>) -> bool { + // TODO: implement un-cacheable stores + true + } + #[hdl] + fn process_load_data( + mop: &SimValue, PRegNum>>, + data: &[u8; MAX_LOAD_STORE_SIZE], + ) -> SimValue> { + #[hdl(sim)] + let LoadMOp::<_, _> { load_store_common } = mop; + #[hdl(sim)] + let LoadStoreCommonMOp::<_, _, _> { + common: _, + width, + conversion, + } = load_store_common; + macro_rules! cvt { + ($ty:ident) => { + $ty::from_le_bytes(std::array::from_fn(|i| data[i])) as u64 + }; + } + let int_fp = #[hdl(sim)] + match conversion { + LoadStoreConversion::ZeroExt => + { + #[hdl(sim)] + match width { + LoadStoreWidth::Width8Bit => cvt!(u8), + LoadStoreWidth::Width16Bit => cvt!(u16), + LoadStoreWidth::Width32Bit => cvt!(u32), + LoadStoreWidth::Width64Bit => cvt!(u64), + } + } + LoadStoreConversion::SignExt => + { + #[hdl(sim)] + match width { + LoadStoreWidth::Width8Bit => cvt!(i8), + LoadStoreWidth::Width16Bit => cvt!(i16), + LoadStoreWidth::Width32Bit => cvt!(i32), + LoadStoreWidth::Width64Bit => cvt!(i64), + } + } + }; + let retval = #[hdl(sim)] + PRegValue { + int_fp, + flags: PRegFlags::zeroed_sim(), + }; + retval.into_trace_as_string() + } + #[hdl] + fn process_store_data( + mop: &SimValue, PRegNum>>, + data: u64, + ) -> [Option; MAX_LOAD_STORE_SIZE] { + #[hdl(sim)] + let StoreMOp::<_, _> { load_store_common } = mop; + #[hdl(sim)] + let LoadStoreCommonMOp::<_, _, _> { + common: _, + width, + conversion, + } = load_store_common; + macro_rules! cvt { + ($ty:ident) => {{ + let data = (data as $ty).to_le_bytes(); + std::array::from_fn(|i| data.get(i).copied()) + }}; + } + #[hdl(sim)] + match conversion { + LoadStoreConversion::ZeroExt => + { + #[hdl(sim)] + match width { + LoadStoreWidth::Width8Bit => cvt!(u8), + LoadStoreWidth::Width16Bit => cvt!(u16), + LoadStoreWidth::Width32Bit => cvt!(u32), + LoadStoreWidth::Width64Bit => cvt!(u64), + } + } + LoadStoreConversion::SignExt => + { + #[hdl(sim)] + match width { + LoadStoreWidth::Width8Bit => cvt!(i8), + LoadStoreWidth::Width16Bit => cvt!(i16), + LoadStoreWidth::Width32Bit => cvt!(i32), + LoadStoreWidth::Width64Bit => cvt!(i64), + } + } + } + } + #[hdl] + fn step(&mut self) { + if self.canceling { + return self.canceling_step(); + } + self.d_cache_start = None; + self.d_cache_start_speculative_load = None; + let store_queue_capacity = 4; // TODO: make configurable + struct StoreQueueEntry { + access_range: AddressRange, + data: [u8; MAX_LOAD_STORE_SIZE], + } + let mut store_queue = Vec::::with_capacity(store_queue_capacity); + for op in &mut self.ops { + let access_range = op.access_range(); + let Op { + ref id, + pc: _, + size_in_bytes: _, + ref mop, + is_speculative, + ref src_values, + ref mut dest_value, + sent_cant_cause_cancel: _, + sent_output_ready: _, + ref mut state, + } = *op; + #[hdl(sim)] + match mop { + LoadStoreMOp::<_, _>::Load(mop) => { + let Some([src0, ..]) = src_values else { + continue; + }; + let Ok(access_range) = access_range else { + continue; + }; + let is_cacheable = Self::is_cacheable_load(mop); + let mut blocking_store = false; + for StoreQueueEntry { + access_range: store_range, + data, + } in &store_queue + { + if access_range == *store_range { + // matching load and store -- speculatively forward data + if let OpState::InputNotReady = state + && is_cacheable + { + *state = OpState::FinishedSpeculativeLoad; + *dest_value = Some(Self::process_load_data(mop, data)); + } + blocking_store = true; + break; + } + if store_range.is_overlapping(access_range) { + blocking_store = true; + break; + } + } + let address = src0.inner().int_fp.as_int(); + let size = LoadStoreWidth::access_byte_size_sim(&mop.load_store_common.width); + let mask = std::array::from_fn(|i| i < size.get() as usize); + match state { + OpState::InputNotReady + if is_speculative && !blocking_store && is_cacheable => + { + self.d_cache_start_speculative_load.get_or_insert_with(|| { + #[hdl(sim)] + DCacheStartSpeculativeLoad::<_> { + id, + address, + mask, + config: self.config, + } + }); + } + OpState::InputNotReady | OpState::FinishedSpeculativeLoad => { + if !is_speculative && dest_value.is_none() { + self.d_cache_start.get_or_insert_with(|| { + #[hdl(sim)] + DCacheStart::<_> { + id, + kind: #[hdl(sim)] + DCacheOpKind.Load( + #[hdl(sim)] + DCacheOpKindLoad { is_cacheable }, + ), + address, + data_and_mask: mask.map(|v| v.then_some(0)), + config: self.config, + } + }); + } + } + OpState::StartedSpeculativeLoad => {} + OpState::StartedLoadStore => {} + OpState::FinishedLoadStore => {} + } + } + LoadStoreMOp::<_, _>::Store(mop) => { + let Op { + ref id, + pc: _, + size_in_bytes: _, + mop: _, + is_speculative, + ref src_values, + ref dest_value, + sent_cant_cause_cancel: _, + sent_output_ready: _, + state, + } = *op; + let Some([src0, src1, ..]) = src_values else { + break; + }; + let Ok(access_range) = access_range else { + continue; + }; + let is_cacheable = Self::is_cacheable_store(mop); + let address = src0.inner().int_fp.as_int(); + let data_and_mask = Self::process_store_data(mop, src1.inner().int_fp.as_int()); + if dest_value.is_none() { + if store_queue.len() >= store_queue_capacity { + break; + } + store_queue.push(StoreQueueEntry { + access_range, + data: data_and_mask.map(|v| v.unwrap_or(0)), + }); + } + match state { + OpState::InputNotReady => { + if !is_speculative { + self.d_cache_start.get_or_insert_with(|| { + #[hdl(sim)] + DCacheStart::<_> { + id, + kind: #[hdl(sim)] + DCacheOpKind.Store( + #[hdl(sim)] + DCacheOpKindStore { is_cacheable }, + ), + address, + data_and_mask, + config: self.config, + } + }); + } + } + OpState::StartedSpeculativeLoad | OpState::FinishedSpeculativeLoad => { + unreachable!() + } + OpState::StartedLoadStore => {} + OpState::FinishedLoadStore => {} + } + } + } + } + } +} + +#[hdl] +async fn load_store_impl( + config: PhantomConst, + unit_index: usize, + filter: SimValue, + cd: Expr, + from_execute: Expr>>, + to_d_cache: Expr>>, + debug_state: Expr>>, + mut sim: ExternModuleSimulationState, +) { + let mut state = LoadStoreState::new(config, unit_index, filter); + loop { + { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state: _, + enqueue, + inputs_ready: _, + is_no_longer_speculative: _, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready: _, + cancel_all, + config: _, + } = from_execute; + sim.write(enqueue.ready, state.from_execute_enqueue_ready()) + .await; + sim.write(cant_cause_cancel, state.from_execute_cant_cause_cancel()) + .await; + sim.write(output_ready, state.from_execute_output_ready()) + .await; + sim.write( + finish_cause_cancel, + state.from_execute_finish_cause_cancel(), + ) + .await; + sim.write(cancel_all.ready, state.from_execute_cancel_all_ready()) + .await; + } + { + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line: _, + config: _, + } = to_d_cache; + sim.write(start.data, &state.d_cache_start).await; + sim.write(finish.ready, state.to_d_cache_finish_ready()) + .await; + sim.write( + start_speculative_load.data, + &state.d_cache_start_speculative_load, + ) + .await; + sim.write( + finish_speculative_load.ready, + state.to_d_cache_finish_speculative_load_ready(), + ) + .await; + } + sim.write(debug_state, state.debug_state()).await; + sim.wait_for_clock_edge(cd.clk).await; + { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state, + enqueue, + inputs_ready, + is_no_longer_speculative, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready, + cancel_all, + config: _, + } = from_execute; + state.global_state = sim.read_past(global_state, cd.clk).await; + if sim.read_past_bool(enqueue.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(enqueue) = sim.read_past(enqueue.data, cd.clk).await { + state.from_execute_enqueue(enqueue); + } + } + #[hdl(sim)] + if let HdlSome(inputs_ready) = sim.read_past(inputs_ready, cd.clk).await { + state.from_execute_inputs_ready(inputs_ready); + } + #[hdl(sim)] + if let HdlSome(is_no_longer_speculative) = + sim.read_past(is_no_longer_speculative, cd.clk).await + { + state.from_execute_is_no_longer_speculative(is_no_longer_speculative); + } + if sim.read_past_bool(unit_outputs_ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await { + state.from_execute_sent_cant_cause_cancel(cant_cause_cancel); + } + #[hdl(sim)] + if let HdlSome(output_ready) = sim.read_past(output_ready, cd.clk).await { + state.from_execute_sent_output_ready(output_ready); + } + #[hdl(sim)] + if let HdlSome(finish_cause_cancel) = + sim.read_past(finish_cause_cancel, cd.clk).await + { + state.from_execute_sent_finish_cause_cancel(finish_cause_cancel); + } + } + if sim.read_past_bool(cancel_all.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(cancel_all) = sim.read_past(cancel_all.data, cd.clk).await { + #[hdl] + let () = cancel_all; + state.from_execute_cancel_all(); + } + } + } + { + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line, + config: _, + } = to_d_cache; + if sim.read_past_bool(start.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(start) = sim.read_past(start.data, cd.clk).await { + state.to_d_cache_sent_start(start); + } + } + if sim.read_past_bool(finish.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(finish) = sim.read_past(finish.data, cd.clk).await { + state.to_d_cache_finish(finish); + } + } + if sim + .read_past_bool(start_speculative_load.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(start_speculative_load) = + sim.read_past(start_speculative_load.data, cd.clk).await + { + state.to_d_cache_sent_start_speculative_load(start_speculative_load); + } + } + if sim + .read_past_bool(finish_speculative_load.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(finish_speculative_load) = + sim.read_past(finish_speculative_load.data, cd.clk).await + { + state.to_d_cache_finish_speculative_load(finish_speculative_load); + } + } + #[hdl(sim)] + if let HdlSome(foreign_write_to_cache_line) = + sim.read_past(foreign_write_to_cache_line, cd.clk).await + { + state.to_d_cache_foreign_write_to_cache_line(foreign_write_to_cache_line); + } + } + state.step(); + } +} + +#[hdl] +struct LoadStoreFilter { + load: Bool, + store: Bool, +} + +impl LoadStoreFilter { + #[hdl] + fn new( + from_execute: ExecuteToUnitInterface>, + filter: &mut impl RenamedMOpFilter, + ) -> SimValue { + let LoadStoreMOp { Load, Store } = from_execute + .inputs_ready + .HdlSome + .mop + .mop + .inner_ty() + .LoadStore; + #[hdl(sim)] + Self { + load: filter.should_include_ty(Load), + store: filter.should_include_ty(Store), + } + } +} + +#[hdl_module(extern)] +pub fn load_store( + config: PhantomConst, + unit_index: usize, + filter: &mut impl RenamedMOpFilter, +) { + #[hdl] + let cd: ClockDomain = m.input(); + + #[hdl] + let from_execute: ExecuteToUnitInterface> = + m.input(ExecuteToUnitInterface[config]); + + #[hdl] + let to_d_cache: LoadStoreToDCacheInterface> = + m.output(LoadStoreToDCacheInterface[config]); + + #[hdl] + let debug_state: LoadStoreDebugState> = + m.output(LoadStoreDebugState[config]); + + let filter = LoadStoreFilter::new(from_execute.ty(), filter).to_expr(); + + assert_eq!(config.get().units[unit_index].kind, UnitKind::LoadStore); + + m.register_clock_for_past(cd.clk); + + m.extern_module_simulation_fn( + ( + config, + unit_index, + filter, + cd, + from_execute, + to_d_cache, + debug_state, + ), + async |(config, unit_index, filter, cd, from_execute, to_d_cache, debug_state), mut sim| { + let filter = filter.into_sim_value(); + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state: _, + enqueue, + inputs_ready: _, + is_no_longer_speculative: _, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready: _, + cancel_all, + config: _, + } = from_execute; + sim.write(enqueue.ready, false).await; + sim.write(cant_cause_cancel, cant_cause_cancel.ty().HdlNone()) + .await; + sim.write(output_ready, output_ready.ty().HdlNone()).await; + sim.write(finish_cause_cancel, finish_cause_cancel.ty().HdlNone()) + .await; + sim.write(cancel_all.ready, false).await; + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line: _, + config: _, + } = to_d_cache; + sim.write(start.data, start.ty().data.HdlNone()).await; + sim.write(finish.ready, false).await; + sim.write( + debug_state, + LoadStoreState::new(config, unit_index, filter.clone()).debug_state(), + ) + .await; + sim.write( + start_speculative_load.data, + start_speculative_load.ty().data.HdlNone(), + ) + .await; + sim.write(finish_speculative_load.ready, false).await; + sim.write( + debug_state, + LoadStoreState::new(config, unit_index, filter.clone()).debug_state(), + ) + .await; + }, + async |sim, ()| { + load_store_impl( + config, + unit_index, + filter.clone(), + cd, + from_execute, + to_d_cache, + debug_state, + sim, + ) + .await + }, + ) + .await + }, + ); +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub struct LoadStore { + config: PhantomConst, + module: Interned>, +} + +impl LoadStore { + pub fn new( + config: PhantomConst, + unit_index: usize, + filter: &mut impl RenamedMOpFilter, + ) -> Self { + Self { + config, + module: load_store(config, unit_index, filter), + } + } +} + +impl UnitTrait for LoadStore { + type Type = load_store; + + fn ty(&self) -> Self::Type { + self.module.io_ty() + } + + fn unit_kind(&self) -> UnitKind { + UnitKind::LoadStore + } + + fn module(&self) -> Interned> { + self.module + } + + fn io(&self, this: Expr) -> UnitIO { + UnitIO { + cd: Some(this.cd), + from_execute: this.from_execute, + to_d_cache: Some(this.to_d_cache), + } + } + + fn to_dyn(&self) -> DynUnit { + DynUnitWrapper(*self).to_dyn() + } +} diff --git a/crates/cpu/tests/expected/load_store_unit_random.vcd b/crates/cpu/tests/expected/load_store_unit_random.vcd new file mode 100644 index 0000000..9b601df --- /dev/null +++ b/crates/cpu/tests/expected/load_store_unit_random.vcd @@ -0,0 +1,9163 @@ +$timescale 1 ps $end +$scope module load_store_unit_test_harness $end +$scope struct cd $end +$var wire 1 xkA*" clk $end +$var wire 1 zKwks rst $end +$upscope $end +$var wire 1 hfx6* test_passed $end +$var wire 32 cu0TY case_number $end +$scope module load_store $end +$scope struct cd $end +$var wire 1 ax?e' clk $end +$var wire 1 "L17] rst $end +$upscope $end +$scope struct from_execute $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 58uk= \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end +$scope struct enqueue $end +$scope struct data $end +$var string 1 #=V6_ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var wire 8 (na\v fetch_block_id $end +$var wire 16 @X'(B id $end +$var wire 64 ^bMdQ pc $end +$var wire 64 %qIY* predicted_next_pc $end +$var wire 4 @}udv size_in_bytes $end +$var wire 1 b`2eK is_first_mop_in_insn $end +$var wire 1 B9)!F is_last_mop_in_insn $end +$var string 1 'BQom mop $end +$upscope $end +$var string 1 !U-[[ config $end +$upscope $end +$upscope $end +$var wire 1 d7}Pu ready $end +$upscope $end +$scope struct inputs_ready $end +$var string 1 |aoC} \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var wire 8 .k)+D fetch_block_id $end +$var wire 16 UK'F+ \$tag $end +$scope struct HdlSome $end +$var wire 16 \Vkx> id $end +$var string 1 2pTpP config $end +$upscope $end +$upscope $end +$scope struct cant_cause_cancel $end +$var string 1 "C2a \$tag $end +$scope struct HdlSome $end +$var wire 16 KjgNp id $end +$var string 1 &V%NI config $end +$upscope $end +$upscope $end +$scope struct output_ready $end +$var string 1 58@(e \$tag $end +$scope struct HdlSome $end +$var wire 16 Fi"$( id $end +$var string 1 oc*j~ dest_value $end +$scope struct predictor_op $end +$scope struct call_stack_op $end +$var string 1 *ikIo \$tag $end +$var wire 64 (~kip Push $end +$upscope $end +$scope struct cond_br_taken $end +$var string 1 "Z9U( \$tag $end +$var wire 1 AR^gI HdlSome $end +$upscope $end +$var string 1 I('f# config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct finish_cause_cancel $end +$var string 1 `M4,7 \$tag $end +$scope struct HdlSome $end +$var wire 16 k"I,) id $end +$scope struct caused_cancel $end +$var string 1 if,~j \$tag $end +$scope struct HdlSome $end +$var wire 64 F%&y8 start_at_pc $end +$var wire 1 $e)dP cancel_after_retire $end +$var string 1 7dU}| config $end +$upscope $end +$upscope $end +$var string 1 MH1^} config $end +$upscope $end +$upscope $end +$var wire 1 $FGz> unit_outputs_ready $end +$scope struct cancel_all $end +$scope struct data $end +$var string 1 RQ`P= \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 1 H,qS5 ready $end +$upscope $end +$var string 1 *8E3i config $end +$upscope $end +$scope struct to_d_cache $end +$scope struct start $end +$scope struct data $end +$var string 1 clC>\ \$tag $end +$scope struct HdlSome $end +$var wire 16 Fx*hf id $end +$scope struct kind $end +$var string 1 `.bt# \$tag $end +$scope struct Load $end +$var wire 1 rwJ#T is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 |Q==F is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 bn5Z+ address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 iSd"4 \$tag $end +$var wire 8 -Nu*# HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 '^*Wf \$tag $end +$var wire 8 HXJwZ HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 08GK. \$tag $end +$var wire 8 RQyQU HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 N(B:j \$tag $end +$var wire 8 ?Af'; HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 b&;uh \$tag $end +$var wire 8 Z6){- HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 kO6/\ \$tag $end +$var wire 8 setxV HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 Mmj2~ \$tag $end +$var wire 8 sj5Q< HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 .etez \$tag $end +$var wire 8 &5nRS HdlSome $end +$upscope $end +$upscope $end +$var string 1 m)r;: config $end +$upscope $end +$upscope $end +$var wire 1 i:dc. ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 pE[,; \$tag $end +$scope struct HdlSome $end +$var wire 16 Y \[16] $end +$var string 1 b45[] \[17] $end +$var string 1 j9k"{ \[18] $end +$var string 1 !!|oM \[19] $end +$var string 1 ^Kb~e \[20] $end +$var string 1 TVH5C \[21] $end +$var string 1 a[K(Q \[22] $end +$var string 1 qKV.c \[23] $end +$var string 1 |5/x@ \[24] $end +$var string 1 A-K/d \[25] $end +$var string 1 zV_*+ \[26] $end +$var string 1 o%3.( \[27] $end +$var string 1 Ksm6p \[28] $end +$var string 1 M,3^X \[29] $end +$var string 1 kOxV( \[30] $end +$var string 1 *jW=? \[31] $end +$upscope $end +$var wire 1 auAnp canceling $end +$var string 1 yCP%Y config $end +$var string 1 2v%me unit_index $end +$scope struct filter $end +$var wire 1 OM-Jw load $end +$var wire 1 ~-:pg store $end +$upscope $end +$upscope $end +$upscope $end +$scope module mock_d_cache $end +$scope struct cd $end +$var wire 1 LZ.hU clk $end +$var wire 1 moF$Q rst $end +$upscope $end +$scope struct from_load_store $end +$scope struct start $end +$scope struct data $end +$var string 1 4eGZi \$tag $end +$scope struct HdlSome $end +$var wire 16 rz<7> id $end +$scope struct kind $end +$var string 1 upV^> \$tag $end +$scope struct Load $end +$var wire 1 mYJfH is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 FiWM5 is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 'Q]Q6 address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 #ywU7 \$tag $end +$var wire 8 8RW"E HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 9Z$") \$tag $end +$var wire 8 IH+-Q HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 {4d"^ \$tag $end +$var wire 8 \UM5t HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 DuGH \$tag $end +$var wire 8 irtL\ HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 N:S?6 \$tag $end +$var wire 8 [*,"5 HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 Y]~g\ \$tag $end +$var wire 8 e$c_K HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 Djxbz \$tag $end +$var wire 8 3:WPC HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 h+/@a \$tag $end +$var wire 8 $/Y&F HdlSome $end +$upscope $end +$upscope $end +$var string 1 VZ=1m config $end +$upscope $end +$upscope $end +$var wire 1 hsyYk ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 A2!N3 \[0] $end +$var wire 8 :3`Bt \[1] $end +$var wire 8 [r9i6 \[2] $end +$var wire 8 *qqWO \[3] $end +$var wire 8 4bC~O \[4] $end +$var wire 8 ~#NBul \[11] $end +$var string 1 A#*8c \[12] $end +$var string 1 UI2FT \[13] $end +$var string 1 }Y8IE \[14] $end +$var string 1 [Wp~< \[15] $end +$var string 1 hOz.a \[16] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct debug_state $end +$scope struct memory_state $end +$scope struct io $end +$var string 1 +j*Nj \[0] $end +$var string 1 !0A#" \[1] $end +$var string 1 qobV: \[2] $end +$var string 1 p0M]( \[3] $end +$var string 1 '_5hF \[4] $end +$var string 1 `)?r+ \[5] $end +$var string 1 omv'r \[6] $end +$var string 1 ,)$b| \[7] $end +$upscope $end +$scope struct cacheable $end +$var string 1 ?:p>( \[0] $end +$var string 1 )[?.c \[1] $end +$var string 1 N(YUR \[2] $end +$var string 1 BTqW) \[3] $end +$var string 1 HoEE/ \[4] $end +$var string 1 iY_WD \[5] $end +$var string 1 "s4C[ \[6] $end +$var string 1 JI[~l \[7] $end +$var string 1 HA!'h \[8] $end +$var string 1 n}([| \[9] $end +$var string 1 "iZfJ \[10] $end +$var string 1 (cgej \[11] $end +$var string 1 9+r9/ \[12] $end +$var string 1 <"{p. \[13] $end +$var string 1 Q&Z%C \[14] $end +$var string 1 Y.ICT \[15] $end +$var string 1 iyAzi \[16] $end +$upscope $end +$upscope $end +$scope struct cache_line_addresses $end +$var string 1 ./T%f \[0] $end +$var string 1 DPs[r \[1] $end +$var string 1 Q*>~n \[2] $end +$var string 1 i:mWN \[3] $end +$var string 1 Fy:4U \[4] $end +$var string 1 EJ^mU \[5] $end +$var string 1 9P]*e \[6] $end +$var string 1 iys*D \[7] $end +$var string 1 {;]Eg \[8] $end +$var string 1 gIPW& \[9] $end +$var string 1 .i:'{ \[10] $end +$var string 1 $gaUw \[11] $end +$var string 1 2V";J \[12] $end +$var string 1 \#>Mw \[13] $end +$var string 1 SE"eg \[14] $end +$var string 1 {/D;z \[15] $end +$upscope $end +$scope struct load_store_queue $end +$scope struct \[0] $end +$var string 1 ']6!' \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 p}bLv id $end +$scope struct kind $end +$var string 1 Iuua, \$tag $end +$scope struct Load $end +$var wire 1 Ro'&L is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 %B:R/ is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 9|#}} address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 +({Sa \$tag $end +$var wire 8 h/Cz# HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 };m~x \$tag $end +$var wire 8 '|9<4 HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 l6.M@ \$tag $end +$var wire 8 [0g&F HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 gU*|~ \$tag $end +$var wire 8 pW[f@ HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 `l1-, \$tag $end +$var wire 8 Ued^e HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 wgh,X \$tag $end +$var wire 8 {[*`` HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 #(Ahe \$tag $end +$var wire 8 WA3\< HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 `[ifW \$tag $end +$var wire 8 i?DN- HdlSome $end +$upscope $end +$upscope $end +$var string 1 OR^Ki config $end +$upscope $end +$var string 1 i7M'V finish_status $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 C9!@' \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 x&N9, id $end +$scope struct kind $end +$var string 1 RW7m< \$tag $end +$scope struct Load $end +$var wire 1 5ncO% is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 #kJz* is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 U+c(@ address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 T(hzZ \$tag $end +$var wire 8 _fedx HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 06;!D \$tag $end +$var wire 8 3YAH> HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 >zq7z \$tag $end +$var wire 8 c6"$3 HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 i_7k% \$tag $end +$var wire 8 RRdsE HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 khFu$ \$tag $end +$var wire 8 &Fmc* HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 ;F`l- \$tag $end +$var wire 8 :9G#? HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 LWW:~ \$tag $end +$var wire 8 ~m3Gt HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 [$q=A \$tag $end +$var wire 8 0}!?\ HdlSome $end +$upscope $end +$upscope $end +$var string 1 p,.1P config $end +$upscope $end +$var string 1 y?~;g finish_status $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 -oOvx \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 :"@sP id $end +$scope struct kind $end +$var string 1 Ug?!g \$tag $end +$scope struct Load $end +$var wire 1 :[t:m is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 'a10Y is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 c|g@p address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 uvFR- \$tag $end +$var wire 8 _|;jb HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 FDxSm \$tag $end +$var wire 8 UX$>t HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 !fi[w \$tag $end +$var wire 8 x]?1J HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 ;^j#c \$tag $end +$var wire 8 \IPMM HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 y{{/P \$tag $end +$var wire 8 )A0d` HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 n<}\V \$tag $end +$var wire 8 ?qk-x HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 Wb(by \$tag $end +$var wire 8 sy??y HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 /:[W( \$tag $end +$var wire 8 HG{&} HdlSome $end +$upscope $end +$upscope $end +$var string 1 vZY1/ config $end +$upscope $end +$var string 1 <@FC/ finish_status $end +$upscope $end +$upscope $end +$scope struct \[3] $end +$var string 1 h?KBd \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 yzPd \$tag $end +$var wire 8 U-}gQ HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 a\TB[ \$tag $end +$var wire 8 Q;VVh HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 Xbdq= \$tag $end +$var wire 8 nck?s HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 m:3Nb \$tag $end +$var wire 8 @cf[+ HdlSome $end +$upscope $end +$upscope $end +$var string 1 **03E config $end +$upscope $end +$var string 1 \@7D2 finish_status $end +$upscope $end +$upscope $end +$scope struct \[4] $end +$var string 1 4V)d. \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 ~lleg id $end +$scope struct kind $end +$var string 1 3"=Fc \$tag $end +$scope struct Load $end +$var wire 1 [o5?? is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 a%^>m is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 {~q{k address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 zgaHt \$tag $end +$var wire 8 ckekR HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 G\mG4 \$tag $end +$var wire 8 o#XKe HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 \U(03 \$tag $end +$var wire 8 #,wh^ HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 Rk7k? \$tag $end +$var wire 8 Ih`/O HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 "NTw` \$tag $end +$var wire 8 4=dL< HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 ov<[* \$tag $end +$var wire 8 }*qMR HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 ->W{i \$tag $end +$var wire 8 nk.0j HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 2Q3lx \$tag $end +$var wire 8 Ar"j= HdlSome $end +$upscope $end +$upscope $end +$var string 1 [^V>* config $end +$upscope $end +$var string 1 e%v^F finish_status $end +$upscope $end +$upscope $end +$scope struct \[5] $end +$var string 1 ",k>7 \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 *Zw@9 id $end +$scope struct kind $end +$var string 1 .J]iG \$tag $end +$scope struct Load $end +$var wire 1 =9I]{ is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 7V&A| is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 Ln;63 address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 I,yZT \$tag $end +$var wire 8 muSdG HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 :BBbn \$tag $end +$var wire 8 50}q% HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 (l,7: \$tag $end +$var wire 8 Ld~)C HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 4_dG) \$tag $end +$var wire 8 +kG`R HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 \u(f7 \$tag $end +$var wire 8 -leYv HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 DTGPL \$tag $end +$var wire 8 9jP5U HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 |8Wvm \$tag $end +$var wire 8 MsRrY HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 *ked# \$tag $end +$var wire 8 J6KT5 HdlSome $end +$upscope $end +$upscope $end +$var string 1 hn^A\ config $end +$upscope $end +$var string 1 }02#2 finish_status $end +$upscope $end +$upscope $end +$scope struct \[6] $end +$var string 1 SO|I| \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 u=;yr id $end +$scope struct kind $end +$var string 1 /'ron \$tag $end +$scope struct Load $end +$var wire 1 VMI-0 is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 Rg[4t is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 nV(ZL address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 {ZyN: \$tag $end +$var wire 8 X+N4^ HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 "`yC7 \$tag $end +$var wire 8 Wr[zO HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 u_(k9 \$tag $end +$var wire 8 'kN4. HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 0ayF$ \$tag $end +$var wire 8 \e)r- HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 KACOh \$tag $end +$var wire 8 -1p{A HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 p:e37 \$tag $end +$var wire 8 E(JK| HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 YN&Bf \$tag $end +$var wire 8 xC99| HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 NJ_NQ \$tag $end +$var wire 8 %484L HdlSome $end +$upscope $end +$upscope $end +$var string 1 ck??: config $end +$upscope $end +$var string 1 &Cc5M finish_status $end +$upscope $end +$upscope $end +$scope struct \[7] $end +$var string 1 g.vlm \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 8FF/a id $end +$scope struct kind $end +$var string 1 i9q1A \$tag $end +$scope struct Load $end +$var wire 1 At3AR is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 HKhl8 is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 eY5X7 address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 ZD,i# \$tag $end +$var wire 8 &uGwC HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 Q9{sh \$tag $end +$var wire 8 t_YEe HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 *X]T^ \$tag $end +$var wire 8 \E#T= HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 TK4XR \$tag $end +$var wire 8 1-I1Z HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 :(=fe \$tag $end +$var wire 8 oFYY3 HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 :YlX) \$tag $end +$var wire 8 UE!IP HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 $o}K/ \$tag $end +$var wire 8 Me8}, HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 Q6u9` \$tag $end +$var wire 8 ('(PW HdlSome $end +$upscope $end +$upscope $end +$var string 1 [iT6L config $end +$upscope $end +$var string 1 4A*XQ finish_status $end +$upscope $end +$upscope $end +$scope struct \[8] $end +$var string 1 C.M_i \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 l~NpC id $end +$scope struct kind $end +$var string 1 l?^'J \$tag $end +$scope struct Load $end +$var wire 1 ""CQ) is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 ;Y%J} is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 k[b|N address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 iCh8@ \$tag $end +$var wire 8 MuGEJ HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 *])g- \$tag $end +$var wire 8 nu-[) HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 cG5Tw \$tag $end +$var wire 8 x$t)u HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 $>|G@ \$tag $end +$var wire 8 ~"p7a HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 Pw9}f \$tag $end +$var wire 8 %A:L_ HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 Wiih; \$tag $end +$var wire 8 D!`k< HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 kR HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 #WlUA \$tag $end +$var wire 8 w6]Kj HdlSome $end +$upscope $end +$upscope $end +$var string 1 4F's~ config $end +$upscope $end +$var string 1 uW%!H finish_status $end +$upscope $end +$upscope $end +$scope struct \[10] $end +$var string 1 7AY22 \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 x;e-M id $end +$scope struct kind $end +$var string 1 gmx]M \$tag $end +$scope struct Load $end +$var wire 1 J._`f is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 Zl]`I is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 \_jo9 address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 ]V8;f \$tag $end +$var wire 8 2GmsS HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 (=?=e \$tag $end +$var wire 8 tZ_d< HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 3qcBS \$tag $end +$var wire 8 AXn/9 HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 K{N$` \$tag $end +$var wire 8 /p;[{ HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 s^nDK \$tag $end +$var wire 8 RaY#% HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 uR{:U \$tag $end +$var wire 8 @ne'I HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 4;_U_ \$tag $end +$var wire 8 ~Oxn; HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 Ue@@S \$tag $end +$var wire 8 G^[y. HdlSome $end +$upscope $end +$upscope $end +$var string 1 V.EpX config $end +$upscope $end +$var string 1 #dD0f finish_status $end +$upscope $end +$upscope $end +$scope struct \[11] $end +$var string 1 YI/W_ \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 \/QM\ id $end +$scope struct kind $end +$var string 1 DUV@_ \$tag $end +$scope struct Load $end +$var wire 1 Z'\TZ is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 J[lE& is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 ~-RB? address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 +g4Jc \$tag $end +$var wire 8 ms'#] HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 m0Fpu \$tag $end +$var wire 8 +3?m= HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 sD<#4 \$tag $end +$var wire 8 3CS,i HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 Zf6ky \$tag $end +$var wire 8 ,;+XF HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 '-m4^ \$tag $end +$var wire 8 W5xyN HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 CGCuf \$tag $end +$var wire 8 W:mBA HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 rDl;w \$tag $end +$var wire 8 j2y(] HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 @h6r, \$tag $end +$var wire 8 &A5[T HdlSome $end +$upscope $end +$upscope $end +$var string 1 yuH<# config $end +$upscope $end +$var string 1 YC%j* finish_status $end +$upscope $end +$upscope $end +$scope struct \[12] $end +$var string 1 !P(RL \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 J`R9G id $end +$scope struct kind $end +$var string 1 !lKPV \$tag $end +$scope struct Load $end +$var wire 1 @z(.c is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 P#~xX is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 YfBsi address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 dx<0. \$tag $end +$var wire 8 m_FI~ HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 -t"_r \$tag $end +$var wire 8 /GEfE HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 $QYs} \$tag $end +$var wire 8 5MYz^ HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 Fvg}K \$tag $end +$var wire 8 zc0Qe HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 !CE4g \$tag $end +$var wire 8 jl(c` HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 [>P]y \$tag $end +$var wire 8 +[=F_ HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 [U is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 21B4k address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 I:|v2 \$tag $end +$var wire 8 R5@wB HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 Q"X8' \$tag $end +$var wire 8 Yd(@T HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 PEdeA \$tag $end +$var wire 8 yP/Zy HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 %?mR# \$tag $end +$var wire 8 6J5|l HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 i%V#% \$tag $end +$var wire 8 @*\6h HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 @/"R* \$tag $end +$var wire 8 cAh&W HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 oP|w0 \$tag $end +$var wire 8 Sw/Q^ HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 .$~[g \$tag $end +$var wire 8 [\;]d HdlSome $end +$upscope $end +$upscope $end +$var string 1 ,+-pc config $end +$upscope $end +$var string 1 h?FEf finish_status $end +$upscope $end +$upscope $end +$scope struct \[14] $end +$var string 1 %Sl<% \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 |o*T< id $end +$scope struct kind $end +$var string 1 h\];S \$tag $end +$scope struct Load $end +$var wire 1 xGM)p is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 hQMdm is_cacheable $end +$upscope $end +$upscope $end +$var wire 64 f"5|2 address $end +$scope struct data_and_mask $end +$scope struct \[0] $end +$var string 1 tXy$z \$tag $end +$var wire 8 $7{o= HdlSome $end +$upscope $end +$scope struct \[1] $end +$var string 1 .Xi~N \$tag $end +$var wire 8 J;P,^ HdlSome $end +$upscope $end +$scope struct \[2] $end +$var string 1 Cmo5\ \$tag $end +$var wire 8 _'?U^ HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 |P#wI \$tag $end +$var wire 8 H*>=j HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 |cmLH \$tag $end +$var wire 8 ,TskK HdlSome $end +$upscope $end +$scope struct \[5] $end +$var string 1 GW+s\ \$tag $end +$var wire 8 6H}vh HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 Wh4q) \$tag $end +$var wire 8 ,nvNw HdlSome $end +$upscope $end +$scope struct \[7] $end +$var string 1 9vdYA \$tag $end +$var wire 8 Gr?PH HdlSome $end +$upscope $end +$upscope $end +$var string 1 H!8}< config $end +$upscope $end +$var string 1 R~`3l finish_status $end +$upscope $end +$upscope $end +$scope struct \[15] $end +$var string 1 Bxy^/ \$tag $end +$scope struct HdlSome $end +$scope struct op $end +$var wire 16 $u&C7 id $end +$scope struct kind $end +$var string 1 Vu,oQ \$tag $end +$scope struct Load $end +$var wire 1 #H4Q" is_cacheable $end +$upscope $end +$scope struct Store $end +$var wire 1 HdlSome $end +$upscope $end +$scope struct \[3] $end +$var string 1 S^z&z \$tag $end +$var wire 8 @7mX6 HdlSome $end +$upscope $end +$scope struct \[4] $end +$var string 1 $9`D& \$tag $end +$var wire 8 HdlSome $end +$upscope $end +$scope struct \[6] $end +$var string 1 KNl4 \[4] $end +$var wire 1 Vq%h} \[5] $end +$var wire 1 7AvU1 \[6] $end +$var wire 1 Q*CG_ \[7] $end +$upscope $end +$var string 1 c)ux< config $end +$upscope $end +$upscope $end +$scope struct \[1] $end +$var string 1 vudUb \$tag $end +$scope struct HdlSome $end +$var wire 16 +Mf($ id $end +$var wire 64 )D`vK address $end +$scope struct mask $end +$var wire 1 83+<- \[0] $end +$var wire 1 ?zMD9 \[1] $end +$var wire 1 Ssm4Y \[2] $end +$var wire 1 39rXI \[3] $end +$var wire 1 7T-,$ \[4] $end +$var wire 1 @l2B$ \[5] $end +$var wire 1 t?x' \[6] $end +$var wire 1 J%GPn \[7] $end +$upscope $end +$var string 1 dRB/, config $end +$upscope $end +$upscope $end +$scope struct \[2] $end +$var string 1 ,W}r \$tag $end +$scope struct HdlSome $end +$var wire 16 )#>~G id $end +$var wire 64 @u~@P address $end +$scope struct mask $end +$var wire 1 g4k~c \[0] $end +$var wire 1 ,6ahz \[1] $end +$var wire 1 V2n\} \[2] $end +$var wire 1 :[)aw \[3] $end +$var wire 1 G!cR} \[4] $end +$var wire 1 {+NUa \[5] $end +$var wire 1 m;Yrg \[6] $end +$var wire 1 (ODAb \[7] $end +$upscope $end +$var string 1 8ByXj config $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 f*FsO config $end +$upscope $end +$upscope $end +$scope module tester $end +$scope struct cd $end +$var wire 1 l6fEH clk $end +$var wire 1 ^)|R$ rst $end +$upscope $end +$scope struct to_load_store $end +$scope struct global_state $end +$scope struct flags_mode $end +$var string 1 YDv(J \$tag $end +$scope struct PowerISA $end +$upscope $end +$scope struct X86 $end +$upscope $end +$upscope $end +$upscope $end +$scope struct enqueue $end +$scope struct data $end +$var string 1 FWU?{ \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var wire 8 +PWp~ fetch_block_id $end +$var wire 16 ?:G9$ id $end +$var wire 64 SMu,, pc $end +$var wire 64 gxwqA predicted_next_pc $end +$var wire 4 3]8i} size_in_bytes $end +$var wire 1 gl&#R is_first_mop_in_insn $end +$var wire 1 )SsU~ is_last_mop_in_insn $end +$var string 1 MUE.k mop $end +$upscope $end +$var string 1 II|Au config $end +$upscope $end +$upscope $end +$var wire 1 7^H[j ready $end +$upscope $end +$scope struct inputs_ready $end +$var string 1 "j[5p \$tag $end +$scope struct HdlSome $end +$scope struct mop $end +$var wire 8 62=t#E id $end +$var string 1 1{:IZ config $end +$upscope $end +$upscope $end +$scope struct output_ready $end +$var string 1 $R~5` \$tag $end +$scope struct HdlSome $end +$var wire 16 b"rF) id $end +$var string 1 x9z\9 dest_value $end +$scope struct predictor_op $end +$scope struct call_stack_op $end +$var string 1 b0J,S \$tag $end +$var wire 64 ,c?5? Push $end +$upscope $end +$scope struct cond_br_taken $end +$var string 1 MVI0s \$tag $end +$var wire 1 dZ\VI HdlSome $end +$upscope $end +$var string 1 (n~e} config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct finish_cause_cancel $end +$var string 1 7D8"B \$tag $end +$scope struct HdlSome $end +$var wire 16 s'qc@ id $end +$scope struct caused_cancel $end +$var string 1 BGVS2 \$tag $end +$scope struct HdlSome $end +$var wire 64 -gK5b start_at_pc $end +$var wire 1 7d!:p cancel_after_retire $end +$var string 1 O{AmO config $end +$upscope $end +$upscope $end +$var string 1 #ad3) config $end +$upscope $end +$upscope $end +$var wire 1 0VlkI unit_outputs_ready $end +$scope struct cancel_all $end +$scope struct data $end +$var string 1 ?m7)N \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 1 zK}@A ready $end +$upscope $end +$var string 1 5-5`E config $end +$upscope $end +$scope struct from_mock_d_cache $end +$scope struct memory_state $end +$scope struct io $end +$var string 1 i'IPl \[0] $end +$var string 1 (tv>) \[1] $end +$var string 1 y;:r/ \[2] $end +$var string 1 ;3%.z \[3] $end +$var string 1 m5~ \[2] $end +$var string 1 Wi/i@ \[3] $end +$var string 1 kmyz- \[4] $end +$var string 1 3%GG7 \[5] $end +$var string 1 n^+_ \[9] $end +$var string 1 kgo.\ \[10] $end +$var string 1 6wJNU \[11] $end +$var string 1 rE70A \[12] $end +$var string 1 S4_FQ \[13] $end +$var string 1 ]/M4` \[14] $end +$var string 1 %./WK \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 |PzL~ value $end +$var string 1 J[y7" range $end +$upscope $end +$upscope $end +$var string 1 ])RL( enqueued $end +$var wire 1 &_%{d canceling $end +$var string 1 ;z)9q config $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0xkA*" +1zKwks +0hfx6* +b0 cu0TY +0ax?e' +1"L17] +sPowerISA\x20(0) 58uk= +sHdlNone\x20(0) #=V6_ +b0 (na\v +b0 @X'(B +b0 ^bMdQ +b0 %qIY* +b0 @}udv +0b`2eK +0B9)!F +sAddSub\x20pzero,\x20pzero,\x20pzero,\x20pzero,\x200x0_i26 'BQom +sPhantomConst({\"units\":[{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) !U-[[ +0d7}Pu +sHdlNone\x20(0) |aoC} +b0 .k)+D +b0 UK'F+ +b0 \Vkx> +sPhantomConst({\"units\":[{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 2pTpP +sHdlNone\x20(0) "C2a +b0 KjgNp +sPhantomConst({\"units\":[{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) &V%NI +sHdlNone\x20(0) 58@(e +b0 Fi"$( +sPRegValue\x20{\x20int_fp:\x200x0_u64,\x20flags:\x20Pwr\x20{\x20..\x20}\x20} oc*j~ +sNone\x20(0) *ikIo +b0 (~kip +sHdlNone\x20(0) "Z9U( +0AR^gI +sPhantomConst({\"units\":[{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) I('f# +sHdlNone\x20(0) `M4,7 +b0 k"I,) +sHdlNone\x20(0) if,~j +b0 F%&y8 +0$e)dP +sPhantomConst({\"units\":[{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 7dU}| 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+sStore\x20pu0_or0x5,\x20pu1_or0x0,\x20pu1_or0x4,\x200x0_i34,\x20u8 MUE.k +s..5 ])RL( +#346000000 +0xkA*" +0ax?e' +0LZ.hU +0l6fEH +#346500000 +1xkA*" +1ax?e' +1LZ.hU +1l6fEH +s(s)(inr)\x20id=0x5_u16\x20pc=0x1014_u64\x20sz=4:\x20Store\x20pu0_or0x5,\x20pu1_or0x0,\x20pu1_or0x4,\x200x0_i34,\x20u8 !S+5e +b110 (na\v +b110 @X'(B +b1000000011000 ^bMdQ +b1000000011100 %qIY* +sStore\x20pu0_or0x6,\x20pu1_or0x0,\x20pu0_or0x0,\x200x0_i34,\x20s16 'BQom +b110 +PWp~ +b110 ?:G9$ +b1000000011000 SMu,, +b1000000011100 gxwqA +sStore\x20pu0_or0x6,\x20pu1_or0x0,\x20pu0_or0x0,\x200x0_i34,\x20s16 MUE.k +s..6 ])RL( +#347000000 +0xkA*" +0ax?e' +0LZ.hU +0l6fEH +#347500000 +1xkA*" +1ax?e' +1LZ.hU +1l6fEH +s(s)(inr)\x20id=0x6_u16\x20pc=0x1018_u64\x20sz=4:\x20Store\x20pu0_or0x6,\x20pu1_or0x0,\x20pu0_or0x0,\x200x0_i34,\x20s16 27F|r +sHdlNone\x20(0) #=V6_ +b0 (na\v +b0 @X'(B +b0 ^bMdQ +b0 %qIY* +b0 @}udv +0b`2eK +0B9)!F +sAddSub\x20pzero,\x20pzero,\x20pzero,\x20pzero,\x200x0_i26 'BQom +sHdlNone\x20(0) FWU?{ +b0 +PWp~ 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LGPL-3.0-or-later +// See Notices.txt for copyright information + +use cpu::{ + config::{CpuConfig, CpuConfig2PowOutRegNumWidth, PhantomConstCpuConfig, UnitConfig}, + instruction::{ + LoadMOp, LoadStoreConversion, LoadStoreMOp, LoadStoreWidth, PRegNum, StoreMOp, UnitNum, + UnitOutRegNum, + }, + register::{FlagsMode, PRegFlags, PRegFlagsPowerISA, PRegValue}, + rename_execute_retire::{ + ExecuteToUnitInterface, GlobalState, MOpInstance, UnitEnqueue, UnitFinishCauseCancel, + UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady, + }, + unit::{ + UnitKind, + load_store::{ + DCacheFinish, DCacheFinishSpeculativeLoad, DCacheFinishStatus, + DCacheForeignWriteToCacheLine, DCacheOpKind, DCacheOpKindLoad, DCacheOpKindStore, + DCacheStart, DCacheStartSpeculativeLoad, LoadStoreToDCacheInterface, + MAX_LOAD_STORE_SIZE, load_store, + }, + }, + util::array_vec::ArrayVec, +}; +use fayalite::{checked_vcd_output, enum_::EnumType, prelude::*, ty::OpaqueSimValue}; +use serde::{Deserialize, Serialize}; +use std::{ + cell::Cell, + collections::{BTreeMap, VecDeque}, + fmt, + num::NonZeroUsize, + ops::RangeTo, +}; + +fn zeroed(ty: T) -> SimValue { + SimValue::from_opaque( + ty, + OpaqueSimValue::from_bits(UInt::new(ty.canonical().bit_width()).zero()), + ) +} + +#[derive(Default)] +struct RandomState { + state: Cell, +} + +impl RandomState { + fn random_u64(&self, key: u32) -> u64 { + let state = self.state.replace(self.state.get().wrapping_add(1)); + // make a pseudo-random number deterministically based on state and key + let mut random = state + .wrapping_add(1) + .wrapping_mul(0x39FF446D8BFB75BB) // random prime + .rotate_left(32) + .wrapping_mul(0x73161B54984B1C21) // random prime + .rotate_right(60); + random ^= key as u64; + random + .wrapping_mul(0x39FF446D8BFB75BB) // random prime + .rotate_left(32) + .wrapping_mul(0x73161B54984B1C21) // random prime + .rotate_right(60) + } + fn random_enum(&self, ty: T, key: u32) -> SimValue { + let variants = ty.variants(); + let enum_ty = Enum::new(variants); + assert!(!variants.is_empty()); + assert!( + variants.iter().all(|variant| variant.ty.is_none()), + "enum must only have unit variants: {ty:#?}" + ); + let index = self.random_u64(key) as usize % variants.len(); + index + .cast_to(UInt[enum_ty.discriminant_bit_width()]) + .cast_bits_to(ty) + } +} + +macro_rules! make_memory_op_data { + ( + $($Variant:ident([u8; $size:tt]),)* + ) => { + #[derive(Clone, Copy, PartialEq, Eq, Serialize, Deserialize, Hash)] + enum MemoryOpData { + $($Variant([u8; $size]),)* + } + + impl MemoryOpData { + const BYTE_COUNTS: &[usize] = { + let byte_counts = &[$($size),*]; + let mut i = 0; + while i < byte_counts.len() { + assert!(byte_counts[i] == 1 << i); + i += 1; + } + byte_counts + }; + fn try_from_slice(slice: &[u8]) -> Option { + match slice.len() { + $($size => Some(Self::$Variant(<[u8; $size]>::try_from(slice).expect("size known to match"))),)* + _ => None, + } + } + fn as_slice(&self) -> &[u8] { + match self { + $(Self::$Variant(data) => data,)* + } + } + fn as_slice_mut(&mut self) -> &mut [u8] { + match self { + $(Self::$Variant(data) => data,)* + } + } + } + }; +} + +make_memory_op_data! { + Size8([u8; 1]), + Size16([u8; 2]), + Size32([u8; 4]), + Size64([u8; MAX_LOAD_STORE_SIZE]), +} + +impl fmt::Debug for MemoryOpData { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let data = self.as_slice(); + type DataUInt = u64; + let mut value = [0; _]; + value[..data.len()].copy_from_slice(data); + let value = DataUInt::from_le_bytes(value); + let sign_ext_shift = DataUInt::BITS as usize - data.len() * 8; + let signed_value = (value.cast_signed() << sign_ext_shift) >> sign_ext_shift; + write!( + f, + "0x{value:0width$X} ({value}; {signed_value})", + width = data.len() * 2, + ) + } +} + +#[derive(Clone, Copy, PartialEq, Eq, Serialize, Deserialize, Hash)] +enum MemoryIOOp { + Load { address: u64, data: MemoryOpData }, + Store { address: u64, data: MemoryOpData }, +} + +impl fmt::Display for MemoryIOOp { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Load { address, data } => write!(f, "Load {address:#X} -> {data:?}"), + Self::Store { address, data } => write!(f, "Store {address:#X} <- {data:?}"), + } + } +} + +#[derive(Clone, Copy, Serialize, Deserialize, PartialEq, Eq, Hash, Default)] +struct MemoryStateCacheableBlock { + data: [[u8; Self::LINE_SIZE]; Self::LINES], +} + +impl MemoryStateCacheableBlock { + const LINE_SIZE: usize = 16; + const LINES: usize = { + assert!(MemoryState::BLOCK_SIZE.is_multiple_of(Self::LINE_SIZE)); + MemoryState::BLOCK_SIZE / Self::LINE_SIZE + }; + fn fmt_single_line( + address: u64, + line: &[u8; Self::LINE_SIZE], + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + write!(f, "{:#010X}: ", address)?; + for (index, byte) in line.iter().enumerate() { + let spaces = if index > 0 { + index.trailing_zeros().saturating_sub(1) as usize + 1 + } else { + 0 + }; + write!(f, "{:spaces$}{byte:02X}", "")?; + } + Ok(()) + } + fn fmt_line( + address: u64, + expected_address: &mut Option, + indent: &str, + line: &[u8; Self::LINE_SIZE], + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + if expected_address.is_some_and(|v| v != address) { + writeln!(f, "{indent}*")?; + } + f.write_str(indent)?; + Self::fmt_single_line(address, line, f)?; + *expected_address = Some(address.wrapping_add(Self::LINE_SIZE as u64)); + writeln!(f) + } +} + +#[derive(Clone, Serialize, Deserialize, PartialEq, Eq, Hash)] +struct MemoryState { + io: Vec, + cacheable: BTreeMap, +} + +impl MemoryState { + const BLOCK_SIZE: usize = 32; + fn fmt_cacheable( + cacheable: &BTreeMap, + indent: &str, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + let mut expected_address = None; + for (&address, block) in cacheable { + for (i, line) in block.data.iter().enumerate() { + MemoryStateCacheableBlock::fmt_line( + address.wrapping_add(i as u64 * MemoryStateCacheableBlock::LINE_SIZE as u64), + &mut expected_address, + indent, + line, + f, + )?; + } + } + Ok(()) + } + fn fmt_cacheable_single_line( + cacheable: &BTreeMap, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + let mut first = true; + for (&address, block) in cacheable { + for (i, line) in block.data.iter().enumerate() { + if first { + first = false; + } else { + f.write_str("; ")?; + } + MemoryStateCacheableBlock::fmt_single_line( + address.wrapping_add(i as u64 * MemoryStateCacheableBlock::LINE_SIZE as u64), + line, + f, + )?; + } + } + Ok(()) + } +} + +impl fmt::Display for MemoryState { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let MemoryState { io, cacheable } = self; + writeln!(f, "MemoryState {{")?; + for io in io { + writeln!(f, " {io}")?; + } + Self::fmt_cacheable(cacheable, " ", f)?; + write!(f, "}}") + } +} + +impl fmt::Debug for MemoryState { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Display::fmt(self, f) + } +} + +impl MemoryState { + const IO_START: u64 = 0x1_0000_0000; + fn is_cacheable(address: u64) -> bool { + address < Self::IO_START + } + fn split_op( + address: u64, + mut data: [Option; MAX_LOAD_STORE_SIZE], + mut split: impl FnMut(u64, &[u8]), + ) { + let mut splits = [(0, 0, [0; _]); MAX_LOAD_STORE_SIZE]; + let mut splits_len = 0; + for &size in MemoryOpData::BYTE_COUNTS.iter().rev() { + for offset in 0..data.len() { + let split_address = address.wrapping_add(offset as u64); + if split_address.is_multiple_of(size as u64) + && let Some(slice) = data.get_mut(offset..(size + offset)) + { + if slice.iter().all(Option::is_some) { + let data: [u8; MAX_LOAD_STORE_SIZE] = + std::array::from_fn(|i| slice.get(i).copied().flatten().unwrap_or(0)); + splits[splits_len] = (split_address, slice.len(), data); + splits_len += 1; + slice.fill(None); + } + } + } + } + splits[..splits_len].sort_by_key(|&(address, _, _)| address); + for &(address, size, data) in &splits[..splits_len] { + split(address, &data[..size]); + } + } + fn cached_load( + &self, + address: u64, + mask: [bool; MAX_LOAD_STORE_SIZE], + ) -> Option<[u8; MAX_LOAD_STORE_SIZE]> { + const { assert!(Self::BLOCK_SIZE.is_power_of_two()) } + assert_ne!(mask, [false; _]); + if Self::is_cacheable(address) { + let mut retval = [0; MAX_LOAD_STORE_SIZE]; + for (load_offset, mask) in mask.into_iter().enumerate() { + if mask { + let address = address.wrapping_add(load_offset as u64); + assert!(Self::is_cacheable(address), "{address:#X}"); + let block_offset = address % Self::BLOCK_SIZE as u64; + retval[load_offset] = self + .cacheable + .get(&(address - block_offset)) + .map_or(0, |block| block.data.as_flattened()[block_offset as usize]); + } + } + Some(retval) + } else { + None + } + } + fn load( + &mut self, + address: u64, + mask: [bool; MAX_LOAD_STORE_SIZE], + io_bytes: [u8; MAX_LOAD_STORE_SIZE], + ) -> [u8; MAX_LOAD_STORE_SIZE] { + const { assert!(Self::BLOCK_SIZE.is_power_of_two()) } + assert_ne!(mask, [false; _]); + if Self::is_cacheable(address) { + let mut retval = [0; MAX_LOAD_STORE_SIZE]; + for (load_offset, mask) in mask.into_iter().enumerate() { + if mask { + let address = address.wrapping_add(load_offset as u64); + assert!(Self::is_cacheable(address), "{address:#X}"); + let block_offset = address % Self::BLOCK_SIZE as u64; + retval[load_offset] = self + .cacheable + .get(&(address - block_offset)) + .map_or(0, |block| block.data.as_flattened()[block_offset as usize]); + } + } + retval + } else { + let mut retval = [0; MAX_LOAD_STORE_SIZE]; + let mut data = [None; MAX_LOAD_STORE_SIZE]; + for i in 0..MAX_LOAD_STORE_SIZE { + if mask[i] { + retval[i] = io_bytes[i]; + data[i] = Some(io_bytes[i]); + } + } + Self::split_op(address, data, |address, data| { + self.io.push(MemoryIOOp::Load { + address, + data: MemoryOpData::try_from_slice(data).expect("known to be a valid size"), + }); + }); + retval + } + } + fn store(&mut self, address: u64, data: [Option; MAX_LOAD_STORE_SIZE]) { + const { assert!(Self::BLOCK_SIZE.is_power_of_two()) } + assert_ne!(data, [None; _]); + if Self::is_cacheable(address) { + for (store_offset, data) in data.into_iter().enumerate() { + if let Some(data) = data { + let address = address.wrapping_add(store_offset as u64); + assert!(Self::is_cacheable(address), "{address:#X}"); + let block_offset = address % Self::BLOCK_SIZE as u64; + self.cacheable + .entry(address - block_offset) + .or_default() + .data + .as_flattened_mut()[block_offset as usize] = data; + } + } + } else { + Self::split_op(address, data, |address, data| { + self.io.push(MemoryIOOp::Store { + address, + data: MemoryOpData::try_from_slice(data).expect("known to be a valid size"), + }); + }); + } + } + #[track_caller] + fn assert_is_string(&self, expected: &str) { + let s = self.to_string(); + if s != expected { + panic!("state doesn't match: expected: r\"{expected}\"\n\ngot:\nr\"{s}\""); + } + } +} + +impl Default for MemoryState { + fn default() -> Self { + MemoryState { + io: vec![], + cacheable: BTreeMap::new(), + } + } +} + +#[derive(Clone, Serialize, Deserialize, PartialEq, Eq, Hash)] +enum MemorySimStateIOElement { + Single(MemoryIOOp), + EmptyOrRest(Vec), +} + +impl Default for MemorySimStateIOElement { + fn default() -> Self { + Self::EmptyOrRest(vec![]) + } +} + +impl fmt::Display for MemorySimStateIOElement { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Single(op) => fmt::Display::fmt(op, f), + Self::EmptyOrRest(ops) => { + let mut ops = ops.iter(); + if let Some(first) = ops.next() { + fmt::Display::fmt(first, f)?; + for op in ops { + f.write_str("; ")?; + fmt::Display::fmt(op, f)?; + } + Ok(()) + } else { + f.write_str("-") + } + } + } + } +} + +impl fmt::Debug for MemorySimStateIOElement { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Display::fmt(self, f) + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Serialize, Deserialize)] +enum MemorySimStateCacheableElement { + Line { + address: u64, + data: [u8; MemoryStateCacheableBlock::LINE_SIZE], + }, + EmptyOrRest(BTreeMap), +} + +impl Default for MemorySimStateCacheableElement { + fn default() -> Self { + Self::EmptyOrRest(BTreeMap::new()) + } +} + +impl fmt::Display for MemorySimStateCacheableElement { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + &Self::Line { address, ref data } => { + MemoryStateCacheableBlock::fmt_single_line(address, data, f) + } + Self::EmptyOrRest(blocks) => { + if blocks.is_empty() { + f.write_str("-") + } else { + MemoryState::fmt_cacheable_single_line(blocks, f) + } + } + } + } +} + +impl fmt::Debug for MemorySimStateCacheableElement { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Display::fmt(self, f) + } +} + +#[hdl] +struct MemorySimState { + io: Array, { MemoryState::SIM_IO_LEN }>, + cacheable: Array, { MemoryState::SIM_CACHEABLE_LEN }>, +} + +impl MemoryState { + const SIM_IO_LEN: usize = 8; + const SIM_CACHEABLE_LEN: usize = 17; + #[hdl] + fn from_sim_value(value: &::SimValue) -> Self { + #[hdl(sim)] + let MemorySimState { + io, + cacheable: cacheable_in, + } = value; + let mut cacheable: BTreeMap = BTreeMap::new(); + for element in cacheable_in { + match &***element { + MemorySimStateCacheableElement::Line { address, data } => { + let offset = *address % MemoryState::BLOCK_SIZE as u64; + let block_address = address.wrapping_sub(offset); + cacheable + .entry(block_address) + .or_default() + .data + .as_flattened_mut()[offset as usize..] + [..MemoryStateCacheableBlock::LINE_SIZE] + .copy_from_slice(data); + } + MemorySimStateCacheableElement::EmptyOrRest(rest) => { + cacheable.extend(rest.iter().map(|(&address, &block)| (address, block))) + } + } + } + Self { + io: io + .iter() + .flat_map(|io| match &***io { + MemorySimStateIOElement::Single(io) => std::slice::from_ref(io), + MemorySimStateIOElement::EmptyOrRest(io) => io, + }) + .copied() + .collect(), + cacheable, + } + } + #[hdl] + fn to_sim_value(&self) -> SimValue { + let io: [_; Self::SIM_IO_LEN] = std::array::from_fn(|i| { + if i == Self::SIM_IO_LEN - 1 { + SimOnlyValue::new(MemorySimStateIOElement::EmptyOrRest( + self.io.get(i..).unwrap_or(&[]).to_vec(), + )) + } else if let Some(io) = self.io.get(i) { + SimOnlyValue::new(MemorySimStateIOElement::Single(*io)) + } else { + SimOnlyValue::new(MemorySimStateIOElement::EmptyOrRest(vec![])) + } + }); + let mut cacheable = self.cacheable.clone(); + let cacheable: [_; Self::SIM_CACHEABLE_LEN] = std::array::from_fn(|i| { + const { + assert!( + Self::SIM_CACHEABLE_LEN + .strict_sub(1) + .is_multiple_of(MemoryStateCacheableBlock::LINES), + "invalid value of Self::SIM_CACHEABLE_LEN" + ); + } + if i == Self::SIM_CACHEABLE_LEN - 1 { + SimOnlyValue::new(MemorySimStateCacheableElement::EmptyOrRest(std::mem::take( + &mut cacheable, + ))) + } else if let Some((&address, block)) = cacheable.first_key_value() { + let line_index = i % MemoryStateCacheableBlock::LINES; + let offset = line_index * MemoryStateCacheableBlock::LINE_SIZE; + let line = SimOnlyValue::new(MemorySimStateCacheableElement::Line { + address: address.wrapping_add(offset as u64), + data: block.data[line_index], + }); + if line_index == MemoryStateCacheableBlock::LINES - 1 { + cacheable.pop_first(); + } + line + } else { + SimOnlyValue::new(MemorySimStateCacheableElement::EmptyOrRest(BTreeMap::new())) + } + }); + #[hdl(sim)] + MemorySimState { io, cacheable } + } +} + +#[test] +fn test_memory_state() { + let mut state = MemoryState::default(); + assert_eq!( + state.load(0x1000, [true; MAX_LOAD_STORE_SIZE], [0; _]), + [0; _], + ); + state.assert_is_string( + r"MemoryState { +}", + ); + state.store( + 0x1000, + [0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87].map(Some), + ); + state.assert_is_string( + r"MemoryState { + 0x00001000: 80 81 82 83 84 85 86 87 00 00 00 00 00 00 00 00 + 0x00001010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +}", + ); + assert_eq!( + state.load(0x1000, [true; MAX_LOAD_STORE_SIZE], [0; _]), + [0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87], + ); + state.assert_is_string( + r"MemoryState { + 0x00001000: 80 81 82 83 84 85 86 87 00 00 00 00 00 00 00 00 + 0x00001010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +}", + ); + macro_rules! check_load { + ($address:literal, $size:literal, $expected:literal) => {{ + let mut state = MemoryState::default(); + let io_data = [0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87]; + let expected_data = std::array::from_fn(|i| if i < $size { io_data[i] } else { 0 }); + assert_eq!( + state.load($address, std::array::from_fn(|i| i < $size), io_data), + expected_data, + ); + state.assert_is_string($expected); + }}; + } + + // Size 8: + check_load!( + 0x1_0000_0000, + 8, + r"MemoryState { + Load 0x100000000 -> 0x8786858483828180 (9765639646188044672; -8681104427521506944) +}" + ); + check_load!( + 0x1_0000_0001, + 8, + r"MemoryState { + Load 0x100000001 -> 0x80 (128; -128) + Load 0x100000002 -> 0x8281 (33409; -32127) + Load 0x100000004 -> 0x86858483 (2256897155; -2038070141) + Load 0x100000008 -> 0x87 (135; -121) +}" + ); + check_load!( + 0x1_0000_0002, + 8, + r"MemoryState { + Load 0x100000002 -> 0x8180 (33152; -32384) + Load 0x100000004 -> 0x85848382 (2240054146; -2054913150) + Load 0x100000008 -> 0x8786 (34694; -30842) +}" + ); + check_load!( + 0x1_0000_0003, + 8, + r"MemoryState { + Load 0x100000003 -> 0x80 (128; -128) + Load 0x100000004 -> 0x84838281 (2223211137; -2071756159) + Load 0x100000008 -> 0x8685 (34437; -31099) + Load 0x10000000A -> 0x87 (135; -121) +}" + ); + check_load!( + 0x1_0000_0004, + 8, + r"MemoryState { + Load 0x100000004 -> 0x83828180 (2206368128; -2088599168) + Load 0x100000008 -> 0x87868584 (2273740164; -2021227132) +}" + ); + check_load!( + 0x1_0000_0005, + 8, + r"MemoryState { + Load 0x100000005 -> 0x80 (128; -128) + Load 0x100000006 -> 0x8281 (33409; -32127) + Load 0x100000008 -> 0x86858483 (2256897155; -2038070141) + Load 0x10000000C -> 0x87 (135; -121) +}" + ); + check_load!( + 0x1_0000_0006, + 8, + r"MemoryState { + Load 0x100000006 -> 0x8180 (33152; -32384) + Load 0x100000008 -> 0x85848382 (2240054146; -2054913150) + Load 0x10000000C -> 0x8786 (34694; -30842) +}" + ); + check_load!( + 0x1_0000_0007, + 8, + r"MemoryState { + Load 0x100000007 -> 0x80 (128; -128) + Load 0x100000008 -> 0x84838281 (2223211137; -2071756159) + Load 0x10000000C -> 0x8685 (34437; -31099) + Load 0x10000000E -> 0x87 (135; -121) +}" + ); + + // Size 4: + check_load!( + 0x1_0000_0000, + 4, + r"MemoryState { + Load 0x100000000 -> 0x83828180 (2206368128; -2088599168) +}" + ); + check_load!( + 0x1_0000_0001, + 4, + r"MemoryState { + Load 0x100000001 -> 0x80 (128; -128) + Load 0x100000002 -> 0x8281 (33409; -32127) + Load 0x100000004 -> 0x83 (131; -125) +}" + ); + check_load!( + 0x1_0000_0002, + 4, + r"MemoryState { + Load 0x100000002 -> 0x8180 (33152; -32384) + Load 0x100000004 -> 0x8382 (33666; -31870) +}" + ); + check_load!( + 0x1_0000_0003, + 4, + r"MemoryState { + Load 0x100000003 -> 0x80 (128; -128) + Load 0x100000004 -> 0x8281 (33409; -32127) + Load 0x100000006 -> 0x83 (131; -125) +}" + ); + + // Size 2: + check_load!( + 0x1_0000_0000, + 2, + r"MemoryState { + Load 0x100000000 -> 0x8180 (33152; -32384) +}" + ); + check_load!( + 0x1_0000_0001, + 2, + r"MemoryState { + Load 0x100000001 -> 0x80 (128; -128) + Load 0x100000002 -> 0x81 (129; -127) +}" + ); + + // Size 1: + check_load!( + 0x1_0000_0000, + 1, + r"MemoryState { + Load 0x100000000 -> 0x80 (128; -128) +}" + ); +} + +fn get_load_store_unit_index>(config: C) -> usize { + let config = config.get(); + let Some(retval) = config + .units + .iter() + .position(|unit| unit.kind == UnitKind::LoadStore) + else { + panic!("missing UnitKind::LoadStore"); + }; + assert_eq!( + config + .units + .iter() + .rposition(|unit| unit.kind == UnitKind::LoadStore), + Some(retval), + ); + retval +} + +#[hdl] +struct MockDCacheToLoadStoreTester { + memory_state: MemorySimState, +} + +const LOAD_STORE_QUEUE_SIZE: usize = 16; + +#[hdl(no_static)] +struct MockDCacheLoadStoreDebugState> { + op: DCacheStart, + finish_status: TraceAsString>, +} + +#[derive(Debug)] +struct MockDCacheLoadStore { + op: SimValue>, + finish_status: Option>, +} + +#[hdl(no_static)] +struct MockDCacheDebugState> { + memory_state: MemorySimState, + cache_line_addresses: Array>>, 16>, + load_store_queue: Array>, { LOAD_STORE_QUEUE_SIZE }>, + speculative_load_queue: Array>, 3>, + config: C, +} + +struct MockDCacheState<'a, C: PhantomConstCpuConfig> { + memory_state: MemoryState, + cache_line_addresses: [Option; 16], + load_store_queue: VecDeque>, + speculative_load_queue: [Option>>; 3], + config: C, + random_state: &'a RandomState, +} + +impl fmt::Debug for MockDCacheState<'_, C> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + memory_state, + cache_line_addresses, + load_store_queue, + speculative_load_queue, + config, + random_state: _, + } = self; + f.debug_struct("MockDCacheState") + .field("memory_state", memory_state) + .field("cache_line_addresses", cache_line_addresses) + .field("load_store_queue", load_store_queue) + .field("speculative_load_queue", speculative_load_queue) + .field("config", config) + .finish_non_exhaustive() + } +} + +impl<'a, C: PhantomConstCpuConfig> MockDCacheState<'a, C> { + const RANDOM_KEY: u32 = u32::from_be_bytes(*b"MDCS"); + fn new(config: C, random_state: &'a RandomState) -> Self { + Self { + memory_state: MemoryState::default(), + cache_line_addresses: [None; _], + load_store_queue: VecDeque::with_capacity(LOAD_STORE_QUEUE_SIZE), + speculative_load_queue: [const { None }; _], + config, + random_state, + } + } + #[hdl] + fn debug_state(&self) -> SimValue> { + let Self { + ref memory_state, + ref cache_line_addresses, + ref load_store_queue, + ref speculative_load_queue, + config, + random_state: _, + } = *self; + let ret_ty = MockDCacheDebugState[config]; + let load_store_queue: [_; LOAD_STORE_QUEUE_SIZE] = std::array::from_fn(|i| { + let MockDCacheLoadStore { op, finish_status } = load_store_queue.get(i)?; + Some( + #[hdl(sim)] + MockDCacheLoadStoreDebugState::<_> { + op, + finish_status: finish_status.into_trace_as_string(), + }, + ) + }); + #[hdl(sim)] + MockDCacheDebugState::<_> { + memory_state: memory_state.to_sim_value(), + cache_line_addresses: cache_line_addresses.map(|v| v.into_trace_as_string()), + load_store_queue: load_store_queue.into_sim_value_with_type(ret_ty.load_store_queue), + speculative_load_queue: speculative_load_queue + .into_sim_value_with_type(ret_ty.speculative_load_queue), + config, + } + } + #[hdl] + fn from_load_store_start_ready(&self) -> bool { + self.load_store_queue.len() < LOAD_STORE_QUEUE_SIZE + } + #[hdl] + fn handle_from_load_store_start(&mut self, start: SimValue>) { + self.load_store_queue.push_back(MockDCacheLoadStore { + op: start, + finish_status: None, + }); + } + #[hdl] + fn from_load_store_finish_data(&self) -> Option>> { + let MockDCacheLoadStore { op, finish_status } = self.load_store_queue.front()?; + let status = finish_status.as_ref()?; + #[hdl(sim)] + let DCacheStart::<_> { + id, + kind: _, + address: _, + data_and_mask, + config: _, + } = op; + Some( + #[hdl(sim)] + DCacheFinish::<_> { + id, + status, + data: <[_; _]>::clone(data_and_mask).map(|v| { + #[hdl(sim)] + match v { + HdlSome(v) => v, + HdlNone => 0u8.into_sim_value(), + } + }), + config: self.config, + }, + ) + } + #[hdl] + fn handle_from_load_store_finish(&mut self, finish: SimValue>) { + let Some(MockDCacheLoadStore { + op, + finish_status: Some(_), + }) = self.load_store_queue.pop_front() + else { + unreachable!(); + }; + assert_eq!(finish.id, op.id); + } + #[hdl] + fn from_load_store_start_speculative_load_ready(&self) -> bool { + let [.., last] = &self.speculative_load_queue; + last.is_none() + } + #[hdl] + fn handle_from_load_store_start_speculative_load( + &mut self, + start_speculative_load: SimValue>, + ) { + let [.., last] = &mut self.speculative_load_queue; + *last = Some(start_speculative_load); + } + fn do_speculative_load( + &self, + address: u64, + mask: [bool; MAX_LOAD_STORE_SIZE], + ) -> Option<[u8; MAX_LOAD_STORE_SIZE]> { + let cache_line_size = self.config.get().cache_line_size_in_bytes(); + for i in 0..MAX_LOAD_STORE_SIZE { + if mask[i] { + let address = address.wrapping_add(i as u64); + let offset = address % cache_line_size as u64; + let cache_line_address = address.wrapping_sub(offset); + if self + .cache_line_addresses + .contains(&Some(cache_line_address)) + { + assert!( + MemoryState::is_cacheable(address), + "{address:#X} is not cacheable but is in cached line at {cache_line_address:#X}\n{self:#?}" + ); + } + } + } + self.memory_state.cached_load(address, mask) + } + #[hdl] + fn from_load_store_finish_speculative_load_data( + &self, + ) -> Option>> { + let [first, ..] = &self.speculative_load_queue; + #[hdl(sim)] + let DCacheStartSpeculativeLoad::<_> { + id, + address, + mask, + config: _, + } = first.as_ref()?; + let data = self.do_speculative_load(address.as_int(), std::array::from_fn(|i| *mask[i])); + Some( + #[hdl(sim)] + DCacheFinishSpeculativeLoad::<_> { + id, + data, + config: self.config, + }, + ) + } + #[hdl] + fn handle_from_load_store_finish_speculative_load( + &mut self, + finish_speculative_load: SimValue>, + ) { + let [first, ..] = &mut self.speculative_load_queue; + let Some(first) = first.take() else { + unreachable!(); + }; + assert_eq!(first.id, finish_speculative_load.id); + } + #[hdl] + fn from_load_store_foreign_write_to_cache_line( + &self, + ) -> Option>> { + // TODO: implement testing writes from other CPU cores and/or I/O devices once load_store() actually implements that + None + } + #[hdl] + fn to_load_store_tester(&self) -> SimValue { + #[hdl(sim)] + MockDCacheToLoadStoreTester { + memory_state: self.memory_state.to_sim_value(), + } + } + #[hdl] + fn step(&mut self) { + if let [None, ..] = self.speculative_load_queue { + self.speculative_load_queue.rotate_left(1); + } + let mut update_cache_for_access = + |address: u64, + data_and_mask: &[SimValue>>; _], + mut is_cacheable: bool| { + let mut cache_line_addresses = [0; 2]; + let mut cache_line_addresses_len = 0; + for (i, data_and_mask) in data_and_mask.iter().enumerate() { + #[hdl(sim)] + if let HdlNone = data_and_mask { + continue; + } + let address = address.wrapping_add(i as u64); + is_cacheable &= MemoryState::is_cacheable(address); + let offset = address % MemoryState::BLOCK_SIZE as u64; + let cache_line_address = address - offset; + if cache_line_addresses_len == 0 + || cache_line_addresses[cache_line_addresses_len - 1] != cache_line_address + { + cache_line_addresses[cache_line_addresses_len] = cache_line_address; + cache_line_addresses_len += 1; + } + } + let cache_line_addresses = &cache_line_addresses[..cache_line_addresses_len]; + if !is_cacheable { + // flush matching cache lines before doing the access. + // their data is already in self.memory_state, so no need to do a write-back. + for cache_line_address in &mut self.cache_line_addresses { + cache_line_address.take_if(|v| cache_line_addresses.contains(v)); + } + } else { + // insert cache lines before doing the access: + // first, find which new cache lines we need to insert. + let available_space = self + .cache_line_addresses + .iter() + .filter(|v| v.is_none()) + .count(); + let mut new_entries = [0; 2]; + let mut new_entries_len = 0; + for &cache_line_address in cache_line_addresses { + if !self + .cache_line_addresses + .contains(&Some(cache_line_address)) + { + new_entries[new_entries_len] = cache_line_address; + new_entries_len += 1; + } + } + // make space. we have to make space before inserting any new cache lines to avoid + // inserting a cache line and then immediately removing it. + while new_entries_len > available_space { + let evict_index = (self.random_state.random_u64(Self::RANDOM_KEY) + % self.cache_line_addresses.len() as u64) + as usize; + let (before, after) = self.cache_line_addresses.split_at_mut(evict_index); + // search starting at evict_index and wrapping around + let Some(found) = after.iter_mut().chain(before).find(|v| v.is_some()) + else { + unreachable!("can't make enough space"); + }; + *found = None; + } + // add new entries + for &new_entry in &new_entries[..new_entries_len] { + let insert_index = (self.random_state.random_u64(Self::RANDOM_KEY) + % self.cache_line_addresses.len() as u64) + as usize; + // search starting at insert_index and wrapping around + let (before, after) = self.cache_line_addresses.split_at_mut(insert_index); + let Some(found) = after.iter_mut().chain(before).find(|v| v.is_none()) + else { + unreachable!("no free space"); + }; + *found = Some(new_entry); + } + } + }; + for load_store in &mut self.load_store_queue { + let MockDCacheLoadStore { op, finish_status } = load_store; + if finish_status.is_some() { + continue; + } + #[hdl(sim)] + let DCacheStart::<_> { + id: _, + kind, + address, + data_and_mask, + config: _, + } = op; + let address = address.as_int(); + #[hdl(sim)] + match &kind { + DCacheOpKind::Load(kind) => { + #[hdl(sim)] + let DCacheOpKindLoad { is_cacheable } = kind; + update_cache_for_access(address, data_and_mask, **is_cacheable); + // TODO: simulate random memory errors + *finish_status = Some( + #[hdl(sim)] + DCacheFinishStatus.Success(), + ); + let data = self.memory_state.load( + address, + std::array::from_fn(|i| { + #[hdl(sim)] + if let HdlSome(_) = &data_and_mask[i] { + true + } else { + false + } + }), + self.random_state.random_u64(Self::RANDOM_KEY).to_le_bytes(), + ); + for (&data, data_and_mask) in data.iter().zip(data_and_mask) { + #[hdl(sim)] + if let HdlSome(data_and_mask) = data_and_mask { + **data_and_mask = data.into(); + } + } + } + DCacheOpKind::Store(kind) => { + #[hdl(sim)] + let DCacheOpKindStore { is_cacheable } = kind; + update_cache_for_access(address, data_and_mask, **is_cacheable); + // TODO: simulate random memory errors + *finish_status = Some( + #[hdl(sim)] + DCacheFinishStatus.Success(), + ); + self.memory_state.store( + address, + std::array::from_fn(|i| { + #[hdl(sim)] + if let HdlSome(data) = &data_and_mask[i] { + Some(data.as_int()) + } else { + None + } + }), + ); + } + } + break; + } + } +} + +#[hdl] +async fn mock_d_cache_impl( + cd: Expr, + from_load_store: Expr>, + to_load_store_tester: Expr, + debug_state: Expr>, + mut state: MockDCacheState<'_, C>, + mut sim: ExternModuleSimulationState, +) { + loop { + { + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line, + config: _, + } = from_load_store; + sim.write(start.ready, state.from_load_store_start_ready()) + .await; + sim.write(finish.data, state.from_load_store_finish_data()) + .await; + sim.write( + start_speculative_load.ready, + state.from_load_store_start_speculative_load_ready(), + ) + .await; + sim.write( + finish_speculative_load.data, + state.from_load_store_finish_speculative_load_data(), + ) + .await; + sim.write( + foreign_write_to_cache_line, + state.from_load_store_foreign_write_to_cache_line(), + ) + .await; + } + sim.write(to_load_store_tester, state.to_load_store_tester()) + .await; + sim.write(debug_state, state.debug_state()).await; + sim.wait_for_clock_edge(cd.clk).await; + { + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line: _, + config: _, + } = from_load_store; + if sim.read_past_bool(start.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(start) = sim.read_past(start.data, cd.clk).await { + state.handle_from_load_store_start(start); + } + } + if sim.read_past_bool(finish.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(finish) = sim.read_past(finish.data, cd.clk).await { + state.handle_from_load_store_finish(finish); + } + } + if sim + .read_past_bool(start_speculative_load.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(start_speculative_load) = + sim.read_past(start_speculative_load.data, cd.clk).await + { + state.handle_from_load_store_start_speculative_load(start_speculative_load); + } + } + if sim + .read_past_bool(finish_speculative_load.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(finish_speculative_load) = + sim.read_past(finish_speculative_load.data, cd.clk).await + { + state.handle_from_load_store_finish_speculative_load(finish_speculative_load); + } + } + } + state.step(); + } +} + +#[hdl_module(extern)] +fn mock_d_cache(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + + #[hdl] + let from_load_store: LoadStoreToDCacheInterface> = + m.input(LoadStoreToDCacheInterface[config]); + + #[hdl] + let to_load_store_tester: MockDCacheToLoadStoreTester = m.output(); + + #[hdl] + let debug_state: MockDCacheDebugState> = + m.output(MockDCacheDebugState[config]); + + m.register_clock_for_past(cd.clk); + + m.extern_module_simulation_fn( + ( + config, + cd, + from_load_store, + to_load_store_tester, + debug_state, + ), + async |(config, cd, from_load_store, to_load_store_tester, debug_state), mut sim| { + // intentionally have a different sequence each time we're reset + let random_state = RandomState::default(); + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + start_speculative_load, + finish_speculative_load, + foreign_write_to_cache_line, + config: _, + } = from_load_store; + sim.write(start.ready, false).await; + sim.write(finish.data, finish.ty().data.HdlNone()).await; + sim.write(start_speculative_load.ready, false).await; + sim.write( + finish_speculative_load.data, + finish_speculative_load.ty().data.HdlNone(), + ) + .await; + sim.write( + foreign_write_to_cache_line, + foreign_write_to_cache_line.ty().HdlNone(), + ) + .await; + let state = MockDCacheState::new(config, &random_state); + sim.write( + to_load_store_tester, + #[hdl(sim)] + MockDCacheToLoadStoreTester { + memory_state: MemoryState::default().to_sim_value(), + }, + ) + .await; + sim.write(debug_state, state.debug_state()).await; + state + }, + async |sim, state| { + mock_d_cache_impl( + cd, + from_load_store, + to_load_store_tester, + debug_state, + state, + sim, + ) + .await + }, + ) + .await + }, + ); +} + +#[derive(Clone, Debug)] +struct Insn { + cycles_after_start_to_cancel: Option, + mop: SimValue, PRegNum>>>, +} + +impl fmt::Display for Insn { + #[hdl] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + cycles_after_start_to_cancel, + mop, + } = self; + write!(f, "cy_a_s_c=")?; + if let Some(cycles_after_start_to_cancel) = cycles_after_start_to_cancel { + write!(f, "{cycles_after_start_to_cancel}")?; + } else { + write!(f, "None")?; + } + write!(f, ": {:?}", mop.mop) + } +} + +const LOAD_STORE_TESTER_MAX_INSNS: usize = 8; + +#[hdl] +type SimOnlyString = SimOnly; + +#[derive(Clone, PartialEq, Eq, Serialize, Deserialize, Hash)] +#[serde(transparent)] +struct RangeToUsize(RangeTo); + +impl fmt::Debug for RangeToUsize { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.0.fmt(f) + } +} + +impl Default for RangeToUsize { + fn default() -> Self { + Self(..0) + } +} + +#[hdl] +type SimOnlyRangeTo = SimOnly; + +#[hdl(no_static)] +struct LoadStoreTesterDebugState> { + insns: Array, + input_regs: ArrayVec, CpuConfig2PowOutRegNumWidth>, + enqueued: SimOnlyRangeTo, + canceling: Bool, + config: C, +} + +struct LoadStoreTesterState<'a, C: PhantomConstCpuConfig> { + insns: Vec>, + input_regs: Vec>>, + enqueued: RangeTo, + canceling: bool, + config: C, + random_state: &'a RandomState, + load_store_unit_index: usize, + input_unit_index: usize, +} + +impl<'a, C: PhantomConstCpuConfig> LoadStoreTesterState<'a, C> { + const RANDOM_KEY: u32 = u32::from_be_bytes(*b"LSTS"); + #[hdl] + fn new(config: C, random_state: &'a RandomState) -> Self { + let load_store_unit_index = get_load_store_unit_index(config); + let input_unit_index = (load_store_unit_index + 1) % config.get().units.len(); + assert_ne!( + load_store_unit_index, input_unit_index, + "there must be a non-LoadStore unit in the config: {config:#?}", + ); + let num_out_regs = CpuConfig2PowOutRegNumWidth[config]; + assert!( + num_out_regs >= LOAD_STORE_TESTER_MAX_INSNS, + "out_reg_num_width ({}) is too small for there to be enough output registers to fit\n\ + LOAD_STORE_TESTER_MAX_INSNS ({LOAD_STORE_TESTER_MAX_INSNS}): {config:#?}", + config.get().out_reg_num_width, + ); + let insns_len_rand = + random_state.random_u64(Self::RANDOM_KEY) as usize % LOAD_STORE_TESTER_MAX_INSNS.pow(2); + let insns_len = insns_len_rand.isqrt() + 1; + let mut insns = Vec::with_capacity(insns_len); + let mut input_regs = vec![]; + let mut load_outputs: Vec>> = vec![]; + for insn_index in 0..insns_len { + let dest = #[hdl(sim)] + PRegNum::<_> { + unit_num: UnitNum[config].from_index_sim(load_store_unit_index), + unit_out_reg: UnitOutRegNum[config].new_sim(insn_index), + }; + let [src0, src1] = std::array::from_fn(|src_index| { + if load_outputs.is_empty() || random_state.random_u64(Self::RANDOM_KEY) % 2 == 0 { + // use an input + let new_input = input_regs.len() < num_out_regs + && random_state.random_u64(Self::RANDOM_KEY) % 2 == 0; + let input_index; + if new_input || input_regs.is_empty() { + input_index = input_regs.len(); + // if it's src0, then it's an address. also have src1 be an address randomly so addresses read out of memory are valid + let is_address = + src_index == 0 || random_state.random_u64(Self::RANDOM_KEY) % 2 == 0; + let mask = if is_address { + // an address: + // pick between cacheable and I/O + let io_mask = MemoryState::IO_START; + // pick one of 4 cache lines + let cache_line_mask = 3 * MemoryState::BLOCK_SIZE as u64; + // pick a byte in a cache line + let byte_in_cache_line_mask = MemoryState::BLOCK_SIZE as u64 - 1; + io_mask | cache_line_mask | byte_in_cache_line_mask + } else { + // any value + !0 + }; + let value = #[hdl(sim)] + PRegValue { + int_fp: random_state.random_u64(Self::RANDOM_KEY) & mask, + flags: PRegFlags::zeroed_sim(), + }; + input_regs.push(value.into_trace_as_string()); + } else { + input_index = + random_state.random_u64(Self::RANDOM_KEY) as usize % input_regs.len(); + } + #[hdl(sim)] + PRegNum::<_> { + unit_num: UnitNum[config].from_index_sim(input_unit_index), + unit_out_reg: UnitOutRegNum[config].new_sim(input_index), + } + } else { + // use a previous load output + load_outputs[(random_state.random_u64(Self::RANDOM_KEY) + % load_outputs.len() as u64) as usize] + .clone() + } + }); + let width = random_state.random_enum(LoadStoreWidth, Self::RANDOM_KEY); + let conversion = random_state.random_enum(LoadStoreConversion, Self::RANDOM_KEY); + let mop: Expr> = + if random_state.random_u64(Self::RANDOM_KEY) % 2 != 0 { + load_outputs.push(dest.clone()); + LoadMOp::load( + dest, + [&src0].into_sim_value_with_type(Array[src0.ty()][ConstUsize]), + width, + conversion, + ) + } else { + StoreMOp::store( + dest, + [&src0, &src1].into_sim_value_with_type(Array[src0.ty()][ConstUsize]), + width, + conversion, + ) + }; + let pc = 0x1000 + insn_index as u64 * 4; + let cycles_after_start_to_cancel = + NonZeroUsize::new(random_state.random_u64(Self::RANDOM_KEY) as usize % 32) + .filter(|v| v.get() <= 8); + insns.push(Insn { + cycles_after_start_to_cancel, + mop: #[hdl(sim)] + MOpInstance::<_> { + fetch_block_id: insn_index.cast_to_static::>(), + id: insn_index.cast_to_static::>(), + pc, + predicted_next_pc: pc + 4, + size_in_bytes: 4_hdl_u4, + is_first_mop_in_insn: true, + is_last_mop_in_insn: true, + mop: mop.into_trace_as_string(), + }, + }); + } + Self { + insns, + input_regs, + enqueued: ..0, + canceling: false, + config, + random_state, + load_store_unit_index, + input_unit_index, + } + } + #[hdl] + fn debug_state(&self) -> SimValue> { + let Self { + ref insns, + ref input_regs, + ref enqueued, + canceling, + config, + random_state: _, + load_store_unit_index: _, + input_unit_index: _, + } = *self; + let insns = std::array::from_fn(|i| { + SimOnlyValue::new(insns.get(i).map(ToString::to_string).unwrap_or_default()) + }); + let ret_ty = LoadStoreTesterDebugState[config]; + #[hdl(sim)] + LoadStoreTesterDebugState::<_> { + insns, + input_regs: ret_ty + .input_regs + .from_iter_sim(PRegValue::zeroed_sim().into_trace_as_string(), input_regs) + .expect("known to be small enough"), + enqueued: SimOnlyValue::new(RangeToUsize(enqueued.clone())), + canceling, + config, + } + } + #[hdl] + fn to_load_store_unit_outputs_ready(&self) -> bool { + !self.canceling + } + #[hdl] + fn to_load_store_enqueue(&self) -> Option>> { + if self.canceling { + return None; + } + if self.enqueued.end < self.insns.len() { + #[hdl(sim)] + let MOpInstance::<_> { + fetch_block_id, + id, + pc, + predicted_next_pc, + size_in_bytes, + is_first_mop_in_insn, + is_last_mop_in_insn, + mop, + } = &self.insns[self.enqueued.end].mop; + let ret_ty = UnitEnqueue[self.config]; + let mop = #[hdl(sim)] + (ret_ty.mop.mop.inner_ty()).LoadStore(mop.inner()); + Some( + #[hdl(sim)] + UnitEnqueue::<_> { + mop: #[hdl(sim)] + MOpInstance::<_> { + fetch_block_id, + id, + pc, + predicted_next_pc, + size_in_bytes, + is_first_mop_in_insn, + is_last_mop_in_insn, + mop: mop.into_trace_as_string(), + }, + config: self.config, + }, + ) + } else { + None + } + } + #[hdl] + fn handle_to_load_store_enqueue(&mut self, enqueue: SimValue>) { + assert_eq!(self.insns[self.enqueued.end].mop.id, enqueue.mop.id); + self.enqueued.end += 1; + } + #[hdl] + fn to_load_store_inputs_ready(&self) -> Option>> { + return None; + todo!() + } + #[hdl] + fn handle_to_load_store_inputs_ready(&mut self, inputs_ready: SimValue>) { + todo!() + } + #[hdl] + fn to_load_store_is_no_longer_speculative( + &self, + ) -> Option>> { + return None; + todo!() + } + #[hdl] + fn handle_to_load_store_is_no_longer_speculative( + &mut self, + is_no_longer_speculative: SimValue>, + ) { + todo!() + } + #[hdl] + fn handle_to_load_store_cant_cause_cancel( + &mut self, + cant_cause_cancel: SimValue>, + ) { + todo!() + } + #[hdl] + fn handle_to_load_store_output_ready(&mut self, output_ready: SimValue>) { + todo!() + } + #[hdl] + fn handle_to_load_store_finish_cause_cancel( + &mut self, + finish_cause_cancel: SimValue>, + ) { + todo!() + } + #[hdl] + fn to_load_store_cancel_all(&self) -> Option<()> { + return None; + todo!() + } + #[hdl] + fn handle_to_load_store_cancel_all(&mut self) { + todo!() + } + #[hdl] + fn handle_from_mock_d_cache( + &mut self, + from_mock_d_cache: SimValue, + ) { + return; + todo!() + } + #[hdl] + fn test_passed(&self) -> bool { + return false; + todo!() + } + #[hdl] + fn step(&mut self) { + return; + todo!() + } +} + +#[hdl] +async fn load_store_tester_impl( + cd: Expr, + to_load_store: Expr>, + from_mock_d_cache: Expr, + test_passed: Expr, + debug_state: Expr>, + mut state: LoadStoreTesterState<'_, C>, + mut sim: ExternModuleSimulationState, +) { + loop { + { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state: _, + enqueue, + inputs_ready, + is_no_longer_speculative, + cant_cause_cancel: _, + output_ready: _, + finish_cause_cancel: _, + unit_outputs_ready, + cancel_all, + config: _, + } = to_load_store; + let to_load_store_unit_outputs_ready = state.to_load_store_unit_outputs_ready(); + sim.write(unit_outputs_ready, to_load_store_unit_outputs_ready) + .await; + if to_load_store_unit_outputs_ready { + sim.write(enqueue.data, state.to_load_store_enqueue()).await; + sim.write(inputs_ready, state.to_load_store_inputs_ready()) + .await; + sim.write( + is_no_longer_speculative, + state.to_load_store_is_no_longer_speculative(), + ) + .await; + } else { + sim.write(enqueue.data, enqueue.ty().data.HdlNone()).await; + sim.write(inputs_ready, inputs_ready.ty().HdlNone()).await; + sim.write( + is_no_longer_speculative, + is_no_longer_speculative.ty().HdlNone(), + ) + .await; + } + sim.write(cancel_all.data, state.to_load_store_cancel_all()) + .await; + } + sim.write(test_passed, state.test_passed()).await; + sim.write(debug_state, state.debug_state()).await; + sim.wait_for_clock_edge(cd.clk).await; + { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state: _, + enqueue, + inputs_ready, + is_no_longer_speculative, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready, + cancel_all, + config: _, + } = to_load_store; + if sim.read_past_bool(enqueue.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(enqueue) = sim.read_past(enqueue.data, cd.clk).await { + state.handle_to_load_store_enqueue(enqueue); + } + } + #[hdl(sim)] + if let HdlSome(inputs_ready) = sim.read_past(inputs_ready, cd.clk).await { + state.handle_to_load_store_inputs_ready(inputs_ready); + } + #[hdl(sim)] + if let HdlSome(is_no_longer_speculative) = + sim.read_past(is_no_longer_speculative, cd.clk).await + { + state.handle_to_load_store_is_no_longer_speculative(is_no_longer_speculative); + } + if sim.read_past_bool(unit_outputs_ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(cant_cause_cancel) = sim.read_past(cant_cause_cancel, cd.clk).await { + state.handle_to_load_store_cant_cause_cancel(cant_cause_cancel); + } + #[hdl(sim)] + if let HdlSome(output_ready) = sim.read_past(output_ready, cd.clk).await { + state.handle_to_load_store_output_ready(output_ready); + } + #[hdl(sim)] + if let HdlSome(finish_cause_cancel) = + sim.read_past(finish_cause_cancel, cd.clk).await + { + state.handle_to_load_store_finish_cause_cancel(finish_cause_cancel); + } + } + if sim.read_past_bool(cancel_all.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(cancel_all) = sim.read_past(cancel_all.data, cd.clk).await { + #[hdl(sim)] + let () = cancel_all; + state.handle_to_load_store_cancel_all(); + } + } + } + state.handle_from_mock_d_cache(sim.read_past(from_mock_d_cache, cd.clk).await); + state.step(); + } +} + +#[hdl_module(extern)] +fn load_store_tester(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + + #[hdl] + let to_load_store: ExecuteToUnitInterface> = + m.output(ExecuteToUnitInterface[config]); + + #[hdl] + let from_mock_d_cache: MockDCacheToLoadStoreTester = m.input(); + + #[hdl] + let test_passed: Bool = m.output(); + + #[hdl] + let debug_state: LoadStoreTesterDebugState> = + m.output(LoadStoreTesterDebugState[config]); + + m.register_clock_for_past(cd.clk); + + m.extern_module_simulation_fn( + ( + config, + cd, + to_load_store, + from_mock_d_cache, + test_passed, + debug_state, + ), + async |(config, cd, to_load_store, from_mock_d_cache, test_passed, debug_state), + mut sim| { + // intentionally have a different sequence each time we're reset + let random_state = RandomState::default(); + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state, + enqueue, + inputs_ready, + is_no_longer_speculative, + cant_cause_cancel: _, + output_ready: _, + finish_cause_cancel: _, + unit_outputs_ready, + cancel_all, + config: _, + } = to_load_store; + sim.write( + global_state, + #[hdl(sim)] + GlobalState { + flags_mode: FlagsMode.PowerISA( + #[hdl(sim)] + PRegFlagsPowerISA {}, + ), + }, + ) + .await; + sim.write(enqueue.data, enqueue.ty().data.HdlNone()).await; + sim.write(inputs_ready, inputs_ready.ty().HdlNone()).await; + sim.write( + is_no_longer_speculative, + is_no_longer_speculative.ty().HdlNone(), + ) + .await; + sim.write(unit_outputs_ready, false).await; + sim.write(cancel_all.data, HdlNone()).await; + sim.write(test_passed, false).await; + let state = LoadStoreTesterState::new(config, &random_state); + sim.write(debug_state, state.debug_state()).await; + state + }, + async |sim, state| { + load_store_tester_impl( + cd, + to_load_store, + from_mock_d_cache, + test_passed, + debug_state, + state, + sim, + ) + .await + }, + ) + .await + }, + ); +} + +#[hdl_module] +fn load_store_unit_test_harness(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + + #[hdl] + let test_passed: Bool = m.output(); + + // just so the case number ends up in the generated .vcd + #[hdl] + let case_number: UInt<32> = m.input(); + + let _ = case_number; + + #[hdl] + let load_store = instance(load_store(config, 0, &mut ())); + + connect(load_store.cd, cd); + + #[hdl] + let mock_d_cache = instance(mock_d_cache(config)); + + connect(mock_d_cache.cd, cd); + connect(mock_d_cache.from_load_store, load_store.to_d_cache); + + #[hdl] + let tester = instance(load_store_tester(config)); + + connect(tester.cd, cd); + connect(load_store.from_execute, tester.to_load_store); + connect(tester.from_mock_d_cache, mock_d_cache.to_load_store_tester); + connect(test_passed, tester.test_passed); +} + +#[hdl] +#[test] +fn test_load_store_unit_random() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut config = CpuConfig::new( + vec![ + UnitConfig::new(UnitKind::LoadStore), + UnitConfig::new(UnitKind::AluBranch), + ], + NonZeroUsize::new(20).unwrap(), + ); + config.fetch_width = NonZeroUsize::new(2).unwrap(); + let m = load_store_unit_test_harness(PhantomConst::new_sized(config)); + let mut sim = Simulation::new(m); + let _checked_vcd_output = + checked_vcd_output!(&mut sim, "tests/expected/load_store_unit_random.vcd"); + let mut failing_cases = Vec::new(); + for case_number in 0u32..20 { + sim.write(sim.io().case_number, case_number); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + for cycle in 0..20 { + sim.advance_time(SimDuration::from_nanos(500)); + println!("case: {case_number} clock tick: {cycle}"); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + if !sim.read_bool(sim.io().test_passed) { + println!("case: {case_number} failed"); + failing_cases.push(case_number); + } + } + if !failing_cases.is_empty() { + panic!("failing cases: {failing_cases:#?}"); + } +} diff --git a/crates/cpu/tests/units_formal.rs b/crates/cpu/tests/units_formal.rs index fa3397d..2a818b8 100644 --- a/crates/cpu/tests/units_formal.rs +++ b/crates/cpu/tests/units_formal.rs @@ -94,13 +94,17 @@ fn formal_harness( let UnitIO { cd: unit_cd, from_execute: unit_from_execute, + to_d_cache, } = dyn_unit.io(unit); + if let Some(unit_cd) = unit_cd { + connect(unit_cd, cd); + } connect( unit_from_execute, ExecuteToUnitInterfaces::unit_fields(decode_and_run.to_units)[unit_index], ); - if let Some(unit_cd) = unit_cd { - connect(unit_cd, cd); + if let Some(to_d_cache) = to_d_cache { + unimplemented!("to_d_cache for {unit:?}: {to_d_cache:?}"); } } hdl_assert(cd.clk, !decode_and_run.error, "");