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rename_execute_retire: generate l2 stores earlier to make more space in units to increase throughput

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Jacob Lifshay 2026-05-20 17:02:34 -07:00
parent e502dfe574
commit 6026df8d7a
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 54355 additions and 73776 deletions
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20
crates/cpu/src/rename_execute_retire.rs
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@ -1466,11 +1466,21 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
); );
} }
let Some(out_reg_num) = out_reg_num else { let Some(out_reg_num) = out_reg_num else {
println!("try_rename: out_reg_num = None"); let l2_space_available = self.space_available_for_unit(self.l2_reg_file_unit_index);
if self.space_available_for_unit(self.l2_reg_file_unit_index) > 0 let used_unit_out_reg_count = self.rename_table.used_unit_out_reg_count(unit_index);
&& self.rename_table.used_unit_out_reg_count(unit_index) let unit_out_reg_count = 1 << self.config.get().out_reg_num_width;
>= (1 << self.config.get().out_reg_num_width) let threshold_count = (unit_out_reg_count * 3 / 4).clamp(1, unit_out_reg_count);
&& let Some(l2_reg_index) = self.find_free_l2_reg() let free_l2_reg = self.find_free_l2_reg();
println!(
"try_rename: out_reg_num = None \
l2_space_available={l2_space_available} \
used_unit_out_reg_count={used_unit_out_reg_count} \
threshold_count={threshold_count} \
free_l2_reg={free_l2_reg:?}",
);
if l2_space_available > 0
&& used_unit_out_reg_count >= threshold_count
&& let Some(l2_reg_index) = free_l2_reg
{ {
println!("try_rename: start L2 store"); println!("try_rename: start L2 store");
let reg_to_free = LFSR31::next_sim(&mut self.lfsr) as usize let reg_to_free = LFSR31::next_sim(&mut self.lfsr) as usize

128109
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd generated
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2
crates/cpu/tests/rename_execute_retire.rs
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@ -4331,7 +4331,7 @@ fn test_rename_execute_retire_slow_loop() {
}; };
sim.write_clock(sim.io().cd.clk, false); sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true); sim.write_reset(sim.io().cd.rst, true);
for cycle in 0..600 { for cycle in 0..350 {
sim.advance_time(SimDuration::from_nanos(500)); sim.advance_time(SimDuration::from_nanos(500));
println!("clock tick: {cycle}"); println!("clock tick: {cycle}");
sim.write_clock(sim.io().cd.clk, true); sim.write_clock(sim.io().cd.clk, true);