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runs instructions that read other instructions' outputs

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This commit is contained in:
Jacob Lifshay 2025-02-23 19:51:45 -08:00
parent 3bd5c77a3f
commit 5b15f4a6b4
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 29247 additions and 18604 deletions
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47580
crates/cpu/tests/expected/reg_alloc.vcd
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171
crates/cpu/tests/reg_alloc.rs
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@ -47,80 +47,117 @@ fn test_reg_alloc() {
),
},
);
sim.write(
fetch_decode_interface.decoded_insns[0].data,
HdlSome(
let insns = std::array::from_fn::<_, 4, _>(|i| {
MOp.AluBranch(MOp.AluBranch.AddSubI(
#[hdl]
FetchedDecodedMOp {
mop: MOp.AluBranch(MOp.AluBranch.AddSub(
#[hdl]
AddSubMOp {
alu_common: #[hdl]
AluCommonMOp {
common: CommonMOp::new(
0_hdl_u0,
AddSubMOp {
alu_common: #[hdl]
AluCommonMOp {
common: CommonMOp::new(
0_hdl_u0,
#[hdl]
MOpDestReg {
normal_regs: #[hdl]
[
#[hdl]
MOpDestReg {
normal_regs: #[hdl]
[
#[hdl]
MOpRegNum { value: 1u8 },
MOpRegNum::const_zero(),
],
flag_regs: #[hdl]
[HdlSome(()), HdlNone()],
},
[2u8, 3u8, 4u8],
0x1234.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]),
),
output_integer_mode: OutputIntegerMode.Full64(),
MOpRegNum { value: i as u8 + 1 },
MOpRegNum::const_zero(),
],
flag_regs: #[hdl]
[HdlSome(()), HdlNone()],
},
invert_src0: true,
src1_is_carry_in: true,
invert_carry_in: true,
add_pc: true,
},
)),
is_unrelated_pc: true,
pc: 0x1000_hdl_u64,
[0u8; 2],
0x12345678u32.cast_to(SInt[COMMON_MOP_2_IMM_WIDTH]),
),
output_integer_mode: OutputIntegerMode.DupLow32(),
},
invert_src0: false,
src1_is_carry_in: false,
invert_carry_in: false,
add_pc: false,
},
),
);
sim.write(
fetch_decode_interface.decoded_insns[1].data,
HdlSome(
#[hdl]
FetchedDecodedMOp {
mop: MOp.AluBranch(MOp.AluBranch.Logical(
#[hdl]
LogicalMOp {
alu_common: #[hdl]
AluCommonMOp {
common: CommonMOp::new(
0_hdl_u0,
#[hdl]
MOpDestReg {
normal_regs: [
#[hdl]
MOpRegNum { value: 2u8 },
MOpRegNum::const_zero(),
],
flag_regs: [HdlNone(), HdlSome(())],
},
[3u8, 4u8],
SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
),
output_integer_mode: OutputIntegerMode.Full64(),
},
lut: 0b0110_hdl_u4,
))
})
.into_iter()
.chain(
[
MOp.AluBranch(MOp.AluBranch.AddSub(
#[hdl]
AddSubMOp {
alu_common: #[hdl]
AluCommonMOp {
common: CommonMOp::new(
0_hdl_u0,
#[hdl]
MOpDestReg {
normal_regs: #[hdl]
[
#[hdl]
MOpRegNum { value: 1u8 },
MOpRegNum::const_zero(),
],
flag_regs: #[hdl]
[HdlSome(()), HdlNone()],
},
[1u8, 0, 0],
1.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]),
),
output_integer_mode: OutputIntegerMode.Full64(),
},
)),
is_unrelated_pc: false,
pc: 0x1004_hdl_u64,
},
),
invert_src0: false,
src1_is_carry_in: false,
invert_carry_in: false,
add_pc: false,
},
)),
MOp.AluBranch(MOp.AluBranch.Logical(
#[hdl]
LogicalMOp {
alu_common: #[hdl]
AluCommonMOp {
common: CommonMOp::new(
0_hdl_u0,
#[hdl]
MOpDestReg {
normal_regs: [
#[hdl]
MOpRegNum { value: 2u8 },
MOpRegNum::const_zero(),
],
flag_regs: [HdlNone(), HdlSome(())],
},
[2u8, 4u8],
SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
),
output_integer_mode: OutputIntegerMode.Full64(),
},
lut: 0b0110_hdl_u4,
},
)),
]
.into_iter()
.cycle(),
);
let mut insn_index = 0;
for cycle in 0..20 {
for fetch_index in 0..config.fetch_width.get() {
let mop = insns.clone().nth(insn_index).unwrap();
sim.write(
fetch_decode_interface.decoded_insns[fetch_index].data,
HdlSome(
#[hdl]
FetchedDecodedMOp {
mop,
is_unrelated_pc: insn_index == 0,
pc: 0x1000u64 + 4 * insn_index as u64,
},
),
);
insn_index += 1;
}
if cycle == 0 {
insn_index = 0;
}
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));