From 582226c4c0a904059af3cc54447de4c7a6d8b0ec Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 4 Feb 2026 17:55:14 -0800 Subject: [PATCH] added fetch::l1_i_cache -- WIP test --- crates/cpu/src/config.rs | 61 + crates/cpu/src/fetch.rs | 1210 +++ crates/cpu/src/lib.rs | 1 + crates/cpu/src/next_pc.rs | 8 +- crates/cpu/src/util/array_vec.rs | 42 + crates/cpu/tests/expected/fetch.vcd | 10806 ++++++++++++++++++++++++++ crates/cpu/tests/fetch.rs | 651 ++ 7 files changed, 12775 insertions(+), 4 deletions(-) create mode 100644 crates/cpu/src/fetch.rs create mode 100644 crates/cpu/tests/expected/fetch.vcd create mode 100644 crates/cpu/tests/fetch.rs diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index cf2fd08..a9624f3 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -37,6 +37,8 @@ pub struct CpuConfig { pub max_branches_per_fetch: NonZeroUsize, pub max_fetches_in_flight: NonZeroUsize, pub log2_fetch_width_in_bytes: u8, + pub log2_cache_line_size_in_bytes: u8, + pub log2_l1_i_cache_line_count: u8, /// default value for [`UnitConfig::max_in_flight`] pub default_unit_max_in_flight: NonZeroUsize, pub rob_size: NonZeroUsize, @@ -63,6 +65,8 @@ impl CpuConfig { v }; pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; + pub const DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 6; + pub const DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT: u8 = 8; pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = { let Some(v) = NonZeroUsize::new(8) else { unreachable!(); @@ -77,6 +81,8 @@ impl CpuConfig { max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH, max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT, log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES, + log2_cache_line_size_in_bytes: Self::DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES, + log2_l1_i_cache_line_count: Self::DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT, default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT, rob_size, } @@ -141,6 +147,37 @@ impl CpuConfig { .checked_shl(self.log2_fetch_width_in_bytes.into()) .expect("log2_fetch_width_in_bytes is too big") } + pub fn cache_line_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_cache_line_size_in_bytes.into()) + .expect("log2_cache_line_size_in_bytes is too big") + } + pub fn log2_fetches_per_cache_line(&self) -> usize { + self.log2_cache_line_size_in_bytes + .checked_sub(self.log2_fetch_width_in_bytes) + .expect("cache line size in bytes must not be smaller than fetch width in bytes") + .into() + } + pub fn fetches_per_cache_line(&self) -> usize { + self.log2_fetches_per_cache_line() + .try_into() + .ok() + .and_then(|v| 1usize.checked_shl(v)) + .expect("log2_fetches_per_cache_line is too big") + } + pub fn l1_i_cache_line_count(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_line_count.into()) + .expect("log2_l1_i_cache_line_count is too big") + } + pub fn log2_l1_i_cache_size_in_bytes(&self) -> usize { + self.log2_l1_i_cache_line_count as usize + self.log2_cache_line_size_in_bytes as usize + } + pub fn l1_i_cache_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_size_in_bytes() as _) + .expect("L1 I-Cache is too big") + } } #[hdl(get(|c| c.fetch_width.get()))] @@ -161,6 +198,30 @@ pub type CpuConfigLog2FetchWidthInBytes> = DynSize #[hdl(get(|c| c.fetch_width_in_bytes()))] pub type CpuConfigFetchWidthInBytes> = DynSize; +#[hdl(get(|c| c.log2_fetches_per_cache_line()))] +pub type CpuConfigLog2FetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.fetches_per_cache_line()))] +pub type CpuConfigFetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.log2_cache_line_size_in_bytes.into()))] +pub type CpuConfigLog2CacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.cache_line_size_in_bytes()))] +pub type CpuConfigCacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_line_count.into()))] +pub type CpuConfigLog2L1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_line_count()))] +pub type CpuConfigL1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_size_in_bytes()))] +pub type CpuConfigLog2L1ICacheSizeInBytes> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_size_in_bytes()))] +pub type CpuConfigL1ICacheSizeInBytes> = DynSize; + #[hdl(get(|c| c.rob_size.get()))] pub type CpuConfigRobSize> = DynSize; diff --git a/crates/cpu/src/fetch.rs b/crates/cpu/src/fetch.rs new file mode 100644 index 0000000..ea86e7f --- /dev/null +++ b/crates/cpu/src/fetch.rs @@ -0,0 +1,1210 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::{ + CpuConfig, CpuConfigFetchWidthInBytes, CpuConfigFetchesPerCacheLine, + CpuConfigL1ICacheLineCount, CpuConfigLog2FetchWidthInBytes, CpuConfigLog2L1ICacheLineCount, + CpuConfigMaxFetchesInFlight, PhantomConstCpuConfig, + }, + next_pc::{ + FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner, ResetStatus, + ResetSteps, SimValueDefault, + }, + util::array_vec::ArrayVec, +}; +use fayalite::{ + int::{UIntInRangeInclusiveType, UIntInRangeType}, + memory::{ReadWriteStruct, memory_addr_width, splat_mask}, + prelude::*, + util::ready_valid::ReadyValid, +}; +use std::collections::VecDeque; + +#[hdl] +pub enum MemoryOperationKind { + Read, + Write, +} + +#[hdl(no_static)] +pub struct MemoryOperationStart + PhantomConstCpuConfig> { + pub kind: MemoryOperationKind, + pub addr: UInt<64>, + pub write_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub fetch_block_id: UInt<8>, // for debugging + pub config: C, +} + +#[hdl] +pub enum MemoryOperationErrorKind { + Generic, +} + +#[hdl] +pub enum MemoryOperationFinishKind { + Success(MemoryOperationKind), + Error(MemoryOperationErrorKind), +} + +#[hdl(no_static)] +pub struct MemoryOperationFinish + PhantomConstCpuConfig> { + pub kind: MemoryOperationFinishKind, + pub read_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub config: C, +} + +#[hdl(no_static)] +pub struct MemoryInterface + PhantomConstCpuConfig> { + pub start: ReadyValid>, + #[hdl(flip)] + pub finish: ReadyValid>, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterfaceInner + PhantomConstCpuConfig> { + pub start_pc: UInt<64>, + pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + pub fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub error: HdlOption, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterface + PhantomConstCpuConfig> { + pub fetched: ReadyValid>, + /// when both fetch and cancel are triggered in the same clock cycle, that means to cancel and then start a new fetch + pub cancel: HdlOption, CpuConfigMaxFetchesInFlight>>, +} + +#[hdl(no_static)] +struct CacheLine + PhantomConstCpuConfig> { + data: ArrayType< + ArrayType, CpuConfigFetchWidthInBytes>, + CpuConfigFetchesPerCacheLine, + >, + addr: HdlOption>>, + config: C, +} + +impl SimValueDefault for CacheLine { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { data, addr, config } = self; + #[hdl(sim)] + Self { + data: data.sim_value_default(), + addr: addr.sim_value_default(), + config, + } + } +} + +#[hdl(get(|c| 64usize.saturating_sub(c.log2_l1_i_cache_size_in_bytes())))] +type CacheLineTagAddrWidth> = DynSize; + +#[hdl] +enum CacheLookupState { + Start, + ReadingCache, + CacheMiss, + Returning, +} + +impl CacheLookupState { + #[hdl] + fn is_empty_if_canceled(this: &SimValue) -> bool { + #[hdl(sim)] + match this { + Self::Start => true, + Self::ReadingCache => false, + Self::CacheMiss => false, + Self::Returning => true, + } + } +} + +#[hdl(no_static)] +struct CacheLineFillIndexesIterator + PhantomConstCpuConfig> { + next_index: HdlOption, CpuConfigFetchesPerCacheLine>>, + config: C, +} + +impl CacheLineFillIndexesIterator { + #[hdl] + fn empty(self) -> SimValue { + #[hdl(sim)] + Self { + next_index: #[hdl(sim)] + (self.next_index).HdlNone(), + config: self.config, + } + } + #[hdl] + fn full(self) -> SimValue { + #[hdl(sim)] + Self { + next_index: #[hdl(sim)] + (self.next_index).HdlSome(0usize), + config: self.config, + } + } + #[hdl] + fn is_empty(this: &SimValue) -> bool { + #[hdl(sim)] + let Self { + next_index, + config: _, + } = this; + #[hdl(sim)] + match next_index { + HdlSome(_) => false, + HdlNone => true, + } + } + #[hdl] + fn next_sim( + this: &mut SimValue, + ) -> Option, CpuConfigFetchesPerCacheLine>>> { + #[hdl(sim)] + let Self { + next_index, + config: _, + } = this; + #[hdl(sim)] + match &mut *next_index { + HdlSome(next_index_v) => { + let retval = Some(next_index_v.clone()); + let next = **next_index_v + 1; + if next < next_index_v.ty().end() { + **next_index_v = next; + } else { + *next_index = #[hdl(sim)] + (next_index.ty()).HdlNone(); + } + retval + } + HdlNone => None, + } + } +} + +#[hdl(no_static)] +struct FetchQueueEntry + PhantomConstCpuConfig> { + start_pc: UInt<64>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + state: CacheLookupState, + canceled: Bool, + error: HdlOption, + fill_indexes_to_start: CacheLineFillIndexesIterator, + fill_indexes_to_finish: CacheLineFillIndexesIterator, + fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + config: C, +} + +impl FetchQueueEntry { + #[hdl] + fn is_empty(this: &SimValue) -> bool { + #[hdl(sim)] + let Self { + start_pc: _, + fetch_block_id: _, + state, + canceled, + error: _, + fill_indexes_to_start: _, + fill_indexes_to_finish: _, + fetch_block_data: _, + config: _, + } = this; + CacheLookupState::is_empty_if_canceled(state) && **canceled + } +} + +impl SimValueDefault for FetchQueueEntry { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + start_pc: _, + fetch_block_id, + state: _, + canceled: _, + error: _, + fill_indexes_to_start, + fill_indexes_to_finish, + fetch_block_data, + config, + } = self; + #[hdl(sim)] + Self { + start_pc: 0u64, + fetch_block_id: fetch_block_id.zero(), + state: #[hdl(sim)] + CacheLookupState.Start(), + canceled: true, + error: #[hdl(sim)] + HdlNone(), + fill_indexes_to_start: fill_indexes_to_start.empty(), + fill_indexes_to_finish: fill_indexes_to_finish.empty(), + fetch_block_data: fetch_block_data.sim_value_default(), + config, + } + } +} + +#[hdl(no_static)] +struct L1ICacheState + PhantomConstCpuConfig> { + queue: ArrayVec, CpuConfigMaxFetchesInFlight>, + config: C, +} + +#[derive(Clone, Debug)] +struct L1ICacheStateSim { + queue: VecDeque>>, + state_expr: Expr>, +} + +#[hdl(no_static)] +struct WriteBackStep + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + data: CacheLine, + mask: AsMask>, +} + +#[hdl(no_static)] +struct CacheRead + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + config: C, +} + +#[hdl(no_static)] +struct CacheReadData + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + cache_line: CacheLine, +} + +#[hdl(no_static)] +struct SplitAddr + PhantomConstCpuConfig> { + // fields must be in LSB to MSB order + byte_in_fetch_block: UIntType>, + fetch_block_in_cache_line: UIntInRangeType, CpuConfigFetchesPerCacheLine>, + cache_line_index: UIntType>, + tag: UIntType>, +} + +impl SplitAddr { + #[hdl] + fn split_addr_sim(self, addr: impl ToSimValueWithType>) -> SimValue { + let addr = addr.into_sim_value_with_type(UInt::<64>::new_static()); + assert_eq!( + self.fetch_block_in_cache_line.bit_width(), + self.fetch_block_in_cache_line.end().ilog2() as usize + ); + addr.cast_bits_to(self) + } + #[hdl] + fn addr_sim(this: impl ToSimValue) -> SimValue> { + SimValue::from_dyn_int(this.into_sim_value().cast_to_bits()) + } +} + +struct ReadyForMemoryOperationFinish { + ready_entry_index: usize, +} + +struct ReadyForFetch {} + +impl L1ICacheStateSim { + fn new(state_expr: Expr>) -> Self { + Self { + queue: VecDeque::new(), + state_expr, + } + } + fn config(&self) -> C { + self.state_expr.ty().config + } + #[hdl] + fn try_start_memory_operation(&mut self) -> Option>> { + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + canceled: _, + error, + fill_indexes_to_start, + fill_indexes_to_finish: _, + fetch_block_data: _, + config: _, + } = entry; + #[hdl(sim)] + match state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::Returning => continue, + CacheLookupState::CacheMiss => + { + #[hdl(sim)] + if let HdlSome(_) = error { + continue; + } + } + } + let Some(next_index) = CacheLineFillIndexesIterator::next_sim(fill_indexes_to_start) + else { + continue; + }; + let mem_op_ty = MemoryOperationStart[config]; + let mut addr = SplitAddr[config].split_addr_sim(start_pc); + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index: _, + tag: _, + } = &mut addr; + **byte_in_fetch_block = byte_in_fetch_block.ty().zero(); + *fetch_block_in_cache_line = next_index; + return Some( + #[hdl(sim)] + MemoryOperationStart::<_> { + kind: #[hdl(sim)] + MemoryOperationKind.Read(), + addr: SplitAddr::addr_sim(addr), + write_data: repeat( + mem_op_ty.write_data.element().zero(), + mem_op_ty.write_data.len(), + ), + fetch_block_id, + config, + }, + ); + } + None + } + #[hdl] + fn ready_for_memory_operation_finish(&self) -> Option { + for (ready_entry_index, entry) in self.queue.iter().enumerate() { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc: _, + fetch_block_id: _, + state, + canceled: _, + error: _, + fill_indexes_to_start: _, + fill_indexes_to_finish, + fetch_block_data: _, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::Returning => continue, + CacheLookupState::CacheMiss => {} + } + if CacheLineFillIndexesIterator::is_empty(fill_indexes_to_finish) { + continue; + } + return Some(ReadyForMemoryOperationFinish { ready_entry_index }); + } + None + } + #[must_use] + #[hdl] + fn do_memory_operation_finish<'a>( + &mut self, + ready_for_memory_operation_finish: ReadyForMemoryOperationFinish, + memory_operation_finish: impl ToSimValue>, + ) -> Option>> { + let config = self.config(); + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + canceled: _, + error, + fill_indexes_to_start: _, + fill_indexes_to_finish, + fetch_block_data, + config: _, + } = &mut self.queue[ready_for_memory_operation_finish.ready_entry_index]; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = memory_operation_finish; + let Some(next_index) = CacheLineFillIndexesIterator::next_sim(fill_indexes_to_finish) + else { + unreachable!(); + }; + #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Success(success) => + { + #[hdl(sim)] + match success { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + } + MemoryOperationFinishKind::Error(e) => + { + #[hdl(sim)] + if let HdlNone = &error { + *error = #[hdl(sim)] + HdlSome(e); + } + } + } + let finished = CacheLineFillIndexesIterator::is_empty(fill_indexes_to_finish); + *state = if finished { + #[hdl(sim)] + CacheLookupState.Returning() + } else { + #[hdl(sim)] + CacheLookupState.CacheMiss() + }; + #[hdl(sim)] + if let HdlSome(_) = error { + return None; + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = SplitAddr[config].split_addr_sim(start_pc); + if *fetch_block_in_cache_line == *next_index { + *fetch_block_data = read_data.clone(); + } + let write_back_step_ty = WriteBackStep[config]; + let mut data = write_back_step_ty.data.sim_value_default(); + let mut mask = splat_mask(write_back_step_ty.data, false.to_expr()).into_sim_value(); + #[hdl(sim)] + let AsMask::> { + data: mask_data, + addr: mask_addr, + config: _, + } = &mut mask; + #[hdl(sim)] + let CacheLine::<_> { + data: data_data, + addr: data_addr, + config: _, + } = &mut data; + // set cache line tag, making sure to mark partially-filled cache lines as invalid + **mask_addr = true; + let data_addr_ty = data_addr.ty(); + *data_addr = if finished { + #[hdl(sim)] + data_addr_ty.HdlSome(tag) + } else { + #[hdl(sim)] + data_addr_ty.HdlNone() + }; + data_data[*next_index] = read_data.clone(); + for mask_data_byte in &mut mask_data[*next_index] { + **mask_data_byte = true; + } + Some( + #[hdl(sim)] + WriteBackStep::<_> { + cache_line_index, + data, + mask, + }, + ) + } + #[hdl] + async fn write_debug_state(&self, sim: &mut ExternModuleSimulationState) { + let config = self.config(); + let queue_ty = self.state_expr.ty().queue; + let queue = queue_ty + .from_iter_sim(queue_ty.element().sim_value_default(), &self.queue) + .expect("known to fit"); + sim.write( + self.state_expr, + #[hdl(sim)] + L1ICacheState::<_> { queue, config }, + ) + .await; + } + fn trim_queue(&mut self) { + while let Some(v) = self.queue.back() { + if !FetchQueueEntry::is_empty(v) { + break; + } + self.queue.pop_back(); + } + while let Some(v) = self.queue.front() { + if !FetchQueueEntry::is_empty(v) { + break; + } + self.queue.pop_front(); + } + } + #[hdl] + fn ready_for_fetch(&self) -> Option { + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() <= max_fetches_in_flight); + (self.queue.len() < max_fetches_in_flight).then_some(ReadyForFetch {}) + } + #[hdl] + fn do_fetch<'a>( + &mut self, + ready_for_fetch: ReadyForFetch, + fetch: impl ToSimValue, + ) { + let ReadyForFetch {} = ready_for_fetch; + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() < max_fetches_in_flight); + #[hdl(sim)] + let NextPcToFetchInterfaceInner { + start_pc, + fetch_block_id, + } = fetch; + let entry_ty = FetchQueueEntry[config]; + self.queue.push_back( + #[hdl(sim)] + FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state: #[hdl(sim)] + CacheLookupState.Start(), + canceled: false, + error: #[hdl(sim)] + HdlNone(), + fill_indexes_to_start: entry_ty.fill_indexes_to_start.empty(), + fill_indexes_to_finish: entry_ty.fill_indexes_to_finish.empty(), + fetch_block_data: entry_ty.fetch_block_data.sim_value_default(), + config, + }, + ); + } + #[hdl] + fn cancel_fetches(&mut self, mut in_progress_fetches_to_cancel: usize) { + // cancel in-progress fetches from newest to oldest + for entry in self.queue.iter_mut().rev() { + if in_progress_fetches_to_cancel == 0 { + break; + } + if !*entry.canceled { + *entry.canceled = true; + in_progress_fetches_to_cancel -= 1; + } + } + self.trim_queue(); + } + fn max_cancel_in_fetch(&self) -> usize { + let mut retval = 0; + for entry in &self.queue { + if !*entry.canceled { + retval += 1; + } + } + retval + } + #[must_use] + #[hdl] + fn next_cache_read(&mut self) -> Option>> { + let config = self.config(); + for entry in &mut self.queue { + if FetchQueueEntry::is_empty(entry) { + continue; + } + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + canceled: _, + error: _, + fill_indexes_to_start: _, + fill_indexes_to_finish: _, + fetch_block_data: _, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start => {} + CacheLookupState::ReadingCache => continue, + CacheLookupState::CacheMiss => continue, + CacheLookupState::Returning => continue, + } + *state = #[hdl(sim)] + CacheLookupState.ReadingCache(); + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line: _, + cache_line_index, + tag: _, + } = SplitAddr[config].split_addr_sim(start_pc); + return Some( + #[hdl(sim)] + CacheRead::<_> { + cache_line_index, + config, + }, + ); + } + None + } + #[hdl] + fn cache_read_data(&mut self, cache_read_data: impl ToSimValue>) { + #[hdl(sim)] + let CacheReadData::<_> { + cache_line_index: read_cache_line_index, + cache_line, + } = cache_read_data; + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + canceled: _, + error: _, + fill_indexes_to_start, + fill_indexes_to_finish, + fetch_block_data, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start => continue, + CacheLookupState::ReadingCache => {} + CacheLookupState::CacheMiss => continue, + CacheLookupState::Returning => continue, + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = SplitAddr[config].split_addr_sim(start_pc); + if *cache_line_index.cmp_ne(&read_cache_line_index) { + break; + } + let addr_ty = cache_line.addr.ty(); + let opt_tag = #[hdl(sim)] + addr_ty.HdlSome(tag); + if *opt_tag.cmp_eq(&cache_line.addr) { + // cache hit + *fetch_block_data = cache_line.data[*fetch_block_in_cache_line].clone(); + *state = #[hdl(sim)] + CacheLookupState.Returning(); + } else { + // cache miss + *state = #[hdl(sim)] + CacheLookupState.CacheMiss(); + *fill_indexes_to_start = fill_indexes_to_start.ty().full(); + *fill_indexes_to_finish = fill_indexes_to_finish.ty().full(); + } + break; + } + } + #[hdl] + fn to_decode_fetched(&mut self) -> Option>> { + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + canceled, + error, + fill_indexes_to_start: _, + fill_indexes_to_finish: _, + fetch_block_data, + config, + } = &mut *entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start => continue, + CacheLookupState::ReadingCache => continue, + CacheLookupState::CacheMiss => continue, + CacheLookupState::Returning => {} + } + if **canceled { + continue; + } + let retval = #[hdl(sim)] + FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config, + }; + *entry = entry.ty().sim_value_default(); + return Some(retval); + } + None + } +} + +impl SimValueDefault for L1ICacheState { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { queue, config } = self; + #[hdl(sim)] + Self { + queue: queue.sim_value_default(), + config, + } + } +} + +impl ResetSteps for L1ICacheState { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + // overwritten every cycle, no reset needed + queue: _, + config: _, + } = this; + let _ = step; + ResetStatus::Done + } +} + +#[hdl_module(extern)] +fn l1_i_cache_impl(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode_fetched: ReadyValid>> = + m.output(ReadyValid[FetchToDecodeInterfaceInner[config]]); + #[hdl] + let max_cancel_in_fetch: UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + > = m.output(UIntInRangeInclusiveType[ConstUsize::<0>][CpuConfigMaxFetchesInFlight[config]]); + // i_cache_port.clk is externally overridden with cd.clk + #[hdl] + let i_cache_port: ReadWriteStruct>, DynSize> = m.output( + ReadWriteStruct[CacheLine[config]][memory_addr_width(CpuConfigL1ICacheLineCount[config])], + ); + #[hdl] + let state_for_debug: L1ICacheState> = m.output(L1ICacheState[config]); + m.register_clock_for_past(cd.clk); + #[hdl] + async fn run( + mut sim: ExternModuleSimulationState, + cd: Expr, + memory_interface: Expr>>, + from_next_pc: Expr>>, + to_decode_fetched: Expr>>>, + max_cancel_in_fetch: Expr< + UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + >, + >, + i_cache_port: Expr>, DynSize>>, + state_expr: Expr>>, + ) { + let config = state_expr.ty().config; + let l1_i_cache_line_count = CpuConfigL1ICacheLineCount[config]; + let cache_line_ty = CacheLine[config]; + for step in 0usize..l1_i_cache_line_count { + sim.write(i_cache_port.en, false).await; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, step.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, true.to_expr())) + .await; + sim.wait_for_clock_edge(cd.clk).await; + } + sim.write(from_next_pc.cancel.ready, true).await; + let memory_interface_start_data_ty = memory_interface.start.data.ty(); + let to_decode_fetched_data_ty = to_decode_fetched.data.ty(); + let cache_read_data_ty = CacheReadData[config]; + let mut state = L1ICacheStateSim::new(state_expr); + loop { + state.trim_queue(); + sim.write(from_next_pc.fetch.ready, state.ready_for_fetch().is_some()) + .await; + sim.write( + memory_interface.finish.ready, + state.ready_for_memory_operation_finish().is_some(), + ) + .await; + sim.write( + memory_interface.start.data, + if let Some(v) = state.clone().try_start_memory_operation() { + #[hdl(sim)] + memory_interface_start_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + memory_interface_start_data_ty.HdlNone() + }, + ) + .await; + sim.write( + to_decode_fetched.data, + if let Some(v) = state.clone().to_decode_fetched() { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlNone() + }, + ) + .await; + state.write_debug_state(&mut sim).await; + sim.write(max_cancel_in_fetch, state.max_cancel_in_fetch()) + .await; + sim.wait_for_clock_edge(cd.clk).await; + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + state.try_start_memory_operation(); + } + if sim.read_past_bool(to_decode_fetched.ready, cd.clk).await { + state.to_decode_fetched(); + } + if sim.read_past_bool(i_cache_port.en, cd.clk).await + && !sim.read_past_bool(i_cache_port.wmode, cd.clk).await + { + let addr = sim.read_past(i_cache_port.addr, cd.clk).await; + let cache_line = sim.read_past(i_cache_port.rdata, cd.clk).await; + state.cache_read_data( + #[hdl(sim)] + CacheReadData::<_> { + cache_line_index: addr.cast_to(cache_read_data_ty.cache_line_index), + cache_line, + }, + ); + } + let mut write_back_step = None; + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + let Some(ready_for_memory_operation_finish) = + state.ready_for_memory_operation_finish() + else { + unreachable!(); + }; + #[hdl(sim)] + if let HdlSome(memory_operation_finish) = + sim.read_past(memory_interface.finish.data, cd.clk).await + { + write_back_step = state.do_memory_operation_finish( + ready_for_memory_operation_finish, + memory_operation_finish, + ); + } + } + // handle cancels before pushing new fetch op + if sim.read_past_bool(from_next_pc.cancel.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(in_progress_fetches_to_cancel) = + sim.read_past(from_next_pc.cancel.data, cd.clk).await + { + state.cancel_fetches(*in_progress_fetches_to_cancel); + } + } + if let Some(ready_for_fetch) = state.ready_for_fetch() { + // handle pushing new fetch op after handling cancels + #[hdl(sim)] + if let HdlSome(fetch) = sim.read_past(from_next_pc.fetch.data, cd.clk).await { + state.do_fetch(ready_for_fetch, fetch); + } + } + if let Some(write_back_step) = write_back_step { + #[hdl(sim)] + let WriteBackStep::<_> { + cache_line_index, + data, + mask, + } = write_back_step; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, data).await; + sim.write(wmask, mask).await; + } else if let Some(cache_read) = state.next_cache_read() { + #[hdl] + let CacheRead::<_> { + cache_line_index, + config: _, + } = cache_read; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } else { + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, 0u8.cast_to(addr.ty())).await; + sim.write(en, false).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } + } + } + m.extern_module_simulation_fn( + ( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + |( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + mut sim| async move { + let config = memory_interface.ty().config; + let cache_line_ty = CacheLine[config]; + sim.write(i_cache_port.clk, false).await; // externally overridden with cd.clk, so just write a constant here + sim.resettable( + cd, + |mut sim: ExternModuleSimulationState| async move { + sim.write( + memory_interface.start.data, + memory_interface.ty().start.data.HdlNone(), + ) + .await; + sim.write(memory_interface.finish.ready, false).await; + sim.write( + from_next_pc.next_fetch_block_ids, + from_next_pc.ty().next_fetch_block_ids.HdlNone(), + ) + .await; + sim.write(from_next_pc.fetch.ready, false).await; + sim.write(from_next_pc.cancel.ready, false).await; + sim.write( + to_decode_fetched.data, + to_decode_fetched.ty().data.HdlNone(), + ) + .await; + sim.write(max_cancel_in_fetch, 0usize).await; + sim.write(i_cache_port.addr, 0u8.cast_to(i_cache_port.addr.ty())) + .await; + sim.write(i_cache_port.en, false).await; + sim.write(i_cache_port.wmode, false).await; + sim.write( + i_cache_port.wdata, + CacheLine::sim_value_default(cache_line_ty), + ) + .await; + sim.write( + i_cache_port.wmask, + splat_mask(cache_line_ty, false.to_expr()), + ) + .await; + sim.write(state_for_debug, state_for_debug.ty().sim_value_default()) + .await; + }, + |sim, ()| { + run( + sim, + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ) + }, + ) + .await; + }, + ); +} + +/// implements a direct-mapped L1 I-Cache +#[hdl_module] +pub fn l1_i_cache(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + let cache_line_ty = CacheLine[config]; + let cache_line_count = CpuConfigL1ICacheLineCount[config]; + // TODO: convert to memory with single read/write port once semantics + // for read/write latencies are properly implemented in the simulator: + // https://git.libre-chip.org/libre-chip/fayalite/src/commit/c632e5d570d4763e8e18d764e95b7a9e515ebf99/crates/fayalite/src/sim/compiler.rs#L4774 + // which depends on: + // https://github.com/chipsalliance/firrtl-spec/issues/263 + #[hdl] + let i_cache = reg_builder() + .clock_domain(cd) + .no_reset(ArrayType[cache_line_ty][cache_line_count]); + #[hdl] + let l1_i_cache_impl = instance(l1_i_cache_impl(config)); + connect(l1_i_cache_impl.cd, cd); + connect(memory_interface, l1_i_cache_impl.memory_interface); + connect(l1_i_cache_impl.from_next_pc, from_next_pc); + connect(to_decode.fetched, l1_i_cache_impl.to_decode_fetched); + let to_decode_cancel_ty = to_decode.cancel.ty(); + connect(to_decode.cancel, to_decode_cancel_ty.HdlNone()); + #[hdl] + if from_next_pc.cancel.ready { + #[hdl] + if let HdlSome(cancel) = from_next_pc.cancel.data { + let cancel = cancel.cast_to(UInt[cancel.ty().bit_width()]); + #[hdl] + if cancel.cmp_gt(l1_i_cache_impl.max_cancel_in_fetch) { + connect( + to_decode.cancel, + to_decode_cancel_ty.HdlSome( + (cancel - l1_i_cache_impl.max_cancel_in_fetch.cast_to(cancel.ty())) + .cast_to(to_decode_cancel_ty.HdlSome), + ), + ); + } + } + } + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, + rdata, + wmode, + wdata, + wmask, + } = l1_i_cache_impl.i_cache_port; + connect(rdata, rdata.ty().uninit()); + #[hdl] + if en { + let i_cache_line = i_cache[addr]; + #[hdl] + if wmode { + #[hdl] + let CacheLine::<_> { + data: wdata_data, + addr: wdata_addr, + config: _, + } = wdata; + for ((dest, src), mask) in i_cache_line + .data + .into_iter() + .zip(wdata_data) + .zip(wmask.data) + { + for ((dest, src), mask) in dest.into_iter().zip(src).zip(mask) { + #[hdl] + if mask { + connect(dest, src); + } + } + } + #[hdl] + if wmask.addr { + connect(i_cache_line.addr, wdata_addr); + } + } else { + connect(rdata, i_cache_line); + } + } +} + +#[hdl_module] +pub fn fetch(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let l1_i_cache = instance(l1_i_cache(config)); + connect(l1_i_cache.cd, cd); + connect(memory_interface, l1_i_cache.memory_interface); + connect(l1_i_cache.from_next_pc, from_next_pc); + connect(to_decode, l1_i_cache.to_decode); +} diff --git a/crates/cpu/src/lib.rs b/crates/cpu/src/lib.rs index 7992ec5..62936de 100644 --- a/crates/cpu/src/lib.rs +++ b/crates/cpu/src/lib.rs @@ -2,6 +2,7 @@ // See Notices.txt for copyright information pub mod config; pub mod decoder; +pub mod fetch; pub mod instruction; pub mod next_pc; pub mod powerisa_instructions_xml; diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs index db22f7e..379dbfd 100644 --- a/crates/cpu/src/next_pc.rs +++ b/crates/cpu/src/next_pc.rs @@ -2719,13 +2719,13 @@ impl SimValueDefault for BranchPredictionState { #[derive(Copy, Clone, Debug)] #[must_use] -enum ResetStatus { +pub(crate) enum ResetStatus { Done, Working, } impl ResetStatus { - fn and(self, other: Self) -> Self { + pub(crate) fn and(self, other: Self) -> Self { match (self, other) { (ResetStatus::Done, ResetStatus::Done) => ResetStatus::Done, (ResetStatus::Done | ResetStatus::Working, ResetStatus::Working) @@ -2734,7 +2734,7 @@ impl ResetStatus { } } -trait SimValueDefault: Type { +pub(crate) trait SimValueDefault: Type { fn sim_value_default(self) -> SimValue; } @@ -2828,7 +2828,7 @@ impl SimValueDefault for WipDecodedInsn { } } -trait ResetSteps: Type { +pub(crate) trait ResetSteps: Type { fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus; } diff --git a/crates/cpu/src/util/array_vec.rs b/crates/cpu/src/util/array_vec.rs index 71275b1..b4ac8f0 100644 --- a/crates/cpu/src/util/array_vec.rs +++ b/crates/cpu/src/util/array_vec.rs @@ -2,6 +2,24 @@ // See Notices.txt for copyright information use fayalite::{expr::ops::ExprIndex, int::UIntInRangeInclusiveType, prelude::*}; +use std::fmt; + +#[derive(Clone, Debug)] +pub struct ArrayVecFullError { + pub value: V, + pub rest: std::iter::Chain, I>, +} + +impl fmt::Display for ArrayVecFullError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "ArrayVec is full") + } +} + +impl + fmt::Debug> std::error::Error + for ArrayVecFullError +{ +} #[hdl] pub type Length = UIntInRangeInclusiveType, Max>; @@ -46,6 +64,30 @@ impl ArrayVec { len: self.elements.len().to_sim_value_with_type(self.len), } } + pub fn from_iter_sim>>( + self, + uninit_element: impl ToSimValueWithType, + iter: I, + ) -> Result, ArrayVecFullError, I::IntoIter>> { + let mut value = Self::new_sim(self, uninit_element); + let element = self.element(); + let mut iter = iter.into_iter(); + for i in 0..self.capacity() { + let Some(v) = iter.next() else { + break; + }; + value.elements[i] = v.into_sim_value_with_type(element); + *value.len = i + 1; + } + if let Some(extra) = iter.next() { + Err(ArrayVecFullError { + value, + rest: std::iter::once(extra).chain(iter), + }) + } else { + Ok(value) + } + } pub fn element(self) -> T { self.elements.element() } diff --git a/crates/cpu/tests/expected/fetch.vcd b/crates/cpu/tests/expected/fetch.vcd new file mode 100644 index 0000000..ba0ced6 --- /dev/null +++ b/crates/cpu/tests/expected/fetch.vcd @@ -0,0 +1,10806 @@ +$timescale 1 ps $end +$scope module dut $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 # \$tag $end +$scope struct HdlSome $end +$var wire 64 $ start_pc $end +$var wire 8 % fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 & ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 ' \$tag $end +$scope struct HdlSome $end +$var wire 5 ( value $end +$var string 1 ) range $end +$upscope $end +$upscope $end +$var wire 1 * ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 + \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 , \[0] $end +$var wire 8 - \[1] $end +$var wire 8 . \[2] $end +$var wire 8 / \[3] $end +$var wire 8 0 \[4] $end +$var wire 8 1 \[5] $end +$var wire 8 2 \[6] $end +$var wire 8 3 \[7] $end +$var wire 8 4 \[8] $end +$var wire 8 5 \[9] $end +$var wire 8 6 \[10] $end +$var wire 8 7 \[11] $end +$var wire 8 8 \[12] $end +$var wire 8 9 \[13] $end +$var wire 8 : \[14] $end +$var wire 8 ; \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 < value $end +$var string 1 = range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 > config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 ? \$tag $end +$scope struct HdlSome $end +$var wire 64 @ start_pc $end +$var wire 8 A fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 B \[0] $end +$var wire 8 C \[1] $end +$var wire 8 D \[2] $end +$var wire 8 E \[3] $end +$var wire 8 F \[4] $end +$var wire 8 G \[5] $end +$var wire 8 H \[6] $end +$var wire 8 I \[7] $end +$var wire 8 J \[8] $end +$var wire 8 K \[9] $end +$var wire 8 L \[10] $end +$var wire 8 M \[11] $end +$var wire 8 N \[12] $end +$var wire 8 O \[13] $end +$var wire 8 P \[14] $end +$var wire 8 Q \[15] $end +$upscope $end +$scope struct error $end +$var string 1 R \$tag $end +$var string 1 S HdlSome $end +$upscope $end +$var string 1 T config $end +$upscope $end +$upscope $end +$var wire 1 U ready $end +$upscope $end +$scope struct cancel $end +$var string 1 V \$tag $end +$scope struct HdlSome $end +$var wire 5 W value $end +$var string 1 X range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct fetch $end +$scope struct cd $end +$var wire 1 7A clk $end +$var wire 1 8A rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 9A \$tag $end +$scope struct HdlSome $end +$var string 1 :A kind $end +$var wire 64 ;A addr $end +$scope struct write_data $end +$var wire 8 A \[2] $end +$var wire 8 ?A \[3] $end +$var wire 8 @A \[4] $end +$var wire 8 AA \[5] $end +$var wire 8 BA \[6] $end +$var wire 8 CA \[7] $end +$var wire 8 DA \[8] $end +$var wire 8 EA \[9] $end +$var wire 8 FA \[10] $end +$var wire 8 GA \[11] $end +$var wire 8 HA \[12] $end +$var wire 8 IA \[13] $end +$var wire 8 JA \[14] $end +$var wire 8 KA \[15] $end +$upscope $end +$var string 1 LA config $end +$upscope $end +$upscope $end +$var wire 1 MA ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 NA \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 OA \$tag $end +$var string 1 PA Success $end +$var string 1 QA Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 RA \[0] $end +$var wire 8 SA \[1] $end +$var wire 8 TA \[2] $end +$var wire 8 UA \[3] $end +$var wire 8 VA \[4] $end +$var wire 8 WA \[5] $end +$var wire 8 XA \[6] $end +$var wire 8 YA \[7] $end +$var wire 8 ZA \[8] $end +$var wire 8 [A \[9] $end +$var wire 8 \A \[10] $end +$var wire 8 ]A \[11] $end +$var wire 8 ^A \[12] $end +$var wire 8 _A \[13] $end +$var wire 8 `A \[14] $end +$var wire 8 aA \[15] $end +$upscope $end +$var string 1 bA config $end +$upscope $end +$upscope $end +$var wire 1 cA ready $end +$upscope $end +$var string 1 dA config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 eA \$tag $end +$scope struct HdlSome $end +$var wire 64 fA start_pc $end +$var wire 8 gA fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 hA ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 iA \$tag $end +$scope struct HdlSome $end +$var wire 5 jA value $end +$var string 1 kA range $end +$upscope $end +$upscope $end +$var wire 1 lA ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 mA \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 nA \[0] $end +$var wire 8 oA \[1] $end +$var wire 8 pA \[2] $end +$var wire 8 qA \[3] $end +$var wire 8 rA \[4] $end +$var wire 8 sA \[5] $end +$var wire 8 tA \[6] $end +$var wire 8 uA \[7] $end +$var wire 8 vA \[8] $end +$var wire 8 wA \[9] $end +$var wire 8 xA \[10] $end +$var wire 8 yA \[11] $end +$var wire 8 zA \[12] $end +$var wire 8 {A \[13] $end +$var wire 8 |A \[14] $end +$var wire 8 }A \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 ~A value $end +$var string 1 !B range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 "B config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 #B \$tag $end +$scope struct HdlSome $end +$var wire 64 $B start_pc $end +$var wire 8 %B fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 &B \[0] $end +$var wire 8 'B \[1] $end +$var wire 8 (B \[2] $end +$var wire 8 )B \[3] $end +$var wire 8 *B \[4] $end +$var wire 8 +B \[5] $end +$var wire 8 ,B \[6] $end +$var wire 8 -B \[7] $end +$var wire 8 .B \[8] $end +$var wire 8 /B \[9] $end +$var wire 8 0B \[10] $end +$var wire 8 1B \[11] $end +$var wire 8 2B \[12] $end +$var wire 8 3B \[13] $end +$var wire 8 4B \[14] $end +$var wire 8 5B \[15] $end +$upscope $end +$scope struct error $end +$var string 1 6B \$tag $end +$var string 1 7B HdlSome $end +$upscope $end +$var string 1 8B config $end +$upscope $end +$upscope $end +$var wire 1 9B ready $end +$upscope $end +$scope struct cancel $end +$var string 1 :B \$tag $end +$scope struct HdlSome $end +$var wire 5 ;B value $end +$var string 1 @ \[8] $end +$var wire 8 ?@ \[9] $end +$var wire 8 @@ \[10] $end +$var wire 8 A@ \[11] $end +$var wire 8 B@ \[12] $end +$var wire 8 C@ \[13] $end +$var wire 8 D@ \[14] $end +$var wire 8 E@ \[15] $end +$upscope $end +$var string 1 F@ config $end +$upscope $end +$upscope $end +$var wire 1 G@ ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 H@ \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 I@ \$tag $end +$var string 1 J@ Success $end +$var string 1 K@ Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 L@ \[0] $end +$var wire 8 M@ \[1] $end +$var wire 8 N@ \[2] $end +$var wire 8 O@ \[3] $end +$var wire 8 P@ \[4] $end +$var wire 8 Q@ \[5] $end +$var wire 8 R@ \[6] $end +$var wire 8 S@ \[7] $end +$var wire 8 T@ \[8] $end +$var wire 8 U@ \[9] $end +$var wire 8 V@ \[10] $end +$var wire 8 W@ \[11] $end +$var wire 8 X@ \[12] $end +$var wire 8 Y@ \[13] $end +$var wire 8 Z@ \[14] $end +$var wire 8 [@ \[15] $end +$upscope $end +$var string 1 \@ config $end +$upscope $end +$upscope $end +$var wire 1 ]@ ready $end +$upscope $end +$var string 1 ^@ config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 _@ \$tag $end +$scope struct HdlSome $end +$var wire 64 `@ start_pc $end +$var wire 8 a@ fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 b@ ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 c@ \$tag $end +$scope struct HdlSome $end +$var wire 5 d@ value $end +$var string 1 e@ range $end +$upscope $end +$upscope $end +$var wire 1 f@ ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 g@ \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 h@ \[0] $end +$var wire 8 i@ \[1] $end +$var wire 8 j@ \[2] $end +$var wire 8 k@ \[3] $end +$var wire 8 l@ \[4] $end +$var wire 8 m@ \[5] $end +$var wire 8 n@ \[6] $end +$var wire 8 o@ \[7] $end +$var wire 8 p@ \[8] $end +$var wire 8 q@ \[9] $end +$var wire 8 r@ \[10] $end +$var wire 8 s@ \[11] $end +$var wire 8 t@ \[12] $end +$var wire 8 u@ \[13] $end +$var wire 8 v@ \[14] $end +$var wire 8 w@ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 x@ value $end +$var string 1 y@ range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 z@ config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 {@ \$tag $end +$scope struct HdlSome $end +$var wire 64 |@ start_pc $end +$var wire 8 }@ fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 ~@ \[0] $end +$var wire 8 !A \[1] $end +$var wire 8 "A \[2] $end +$var wire 8 #A \[3] $end +$var wire 8 $A \[4] $end +$var wire 8 %A \[5] $end +$var wire 8 &A \[6] $end +$var wire 8 'A \[7] $end +$var wire 8 (A \[8] $end +$var wire 8 )A \[9] $end +$var wire 8 *A \[10] $end +$var wire 8 +A \[11] $end +$var wire 8 ,A \[12] $end +$var wire 8 -A \[13] $end +$var wire 8 .A \[14] $end +$var wire 8 /A \[15] $end +$upscope $end +$scope struct error $end +$var string 1 0A \$tag $end +$var string 1 1A HdlSome $end +$upscope $end +$var string 1 2A config $end +$upscope $end +$upscope $end +$var wire 1 3A ready $end +$upscope $end +$scope struct cancel $end +$var string 1 4A \$tag $end +$scope struct HdlSome $end +$var wire 5 5A value $end +$var string 1 6A range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module l1_i_cache_2 $end +$scope struct cd $end +$var wire 1 _" clk $end +$var wire 1 `" rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 a" \$tag $end +$scope struct HdlSome $end +$var string 1 b" kind $end +$var wire 64 c" addr $end +$scope struct write_data $end +$var wire 8 d" \[0] $end +$var wire 8 e" \[1] $end +$var wire 8 f" \[2] $end +$var wire 8 g" \[3] $end +$var wire 8 h" \[4] $end +$var wire 8 i" \[5] $end +$var wire 8 j" \[6] $end +$var wire 8 k" \[7] $end +$var wire 8 l" \[8] $end +$var wire 8 m" \[9] $end +$var wire 8 n" \[10] $end +$var wire 8 o" \[11] $end +$var wire 8 p" \[12] $end +$var wire 8 q" \[13] $end +$var wire 8 r" \[14] $end +$var wire 8 s" \[15] $end +$upscope $end +$var string 1 t" config $end +$upscope $end +$upscope $end +$var wire 1 u" ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 v" \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 w" \$tag $end +$var string 1 x" Success $end +$var string 1 y" Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 z" \[0] $end +$var wire 8 {" \[1] $end +$var wire 8 |" \[2] $end +$var wire 8 }" \[3] $end +$var wire 8 ~" \[4] $end +$var wire 8 !# \[5] $end +$var wire 8 "# \[6] $end +$var wire 8 ## \[7] $end +$var wire 8 $# \[8] $end +$var wire 8 %# \[9] $end +$var wire 8 &# \[10] $end +$var wire 8 '# \[11] $end +$var wire 8 (# \[12] $end +$var wire 8 )# \[13] $end +$var wire 8 *# \[14] $end +$var wire 8 +# \[15] $end +$upscope $end +$var string 1 ,# config $end +$upscope $end +$upscope $end +$var wire 1 -# ready $end +$upscope $end +$var string 1 .# config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 /# \$tag $end +$scope struct HdlSome $end +$var wire 64 0# start_pc $end +$var wire 8 1# fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 2# ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 3# \$tag $end +$scope struct HdlSome $end +$var wire 5 4# value $end +$var string 1 5# range $end +$upscope $end +$upscope $end +$var wire 1 6# ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 7# \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 8# \[0] $end +$var wire 8 9# \[1] $end +$var wire 8 :# \[2] $end +$var wire 8 ;# \[3] $end +$var wire 8 <# \[4] $end +$var wire 8 =# \[5] $end +$var wire 8 ># \[6] $end +$var wire 8 ?# \[7] $end +$var wire 8 @# \[8] $end +$var wire 8 A# \[9] $end +$var wire 8 B# \[10] $end +$var wire 8 C# \[11] $end +$var wire 8 D# \[12] $end +$var wire 8 E# \[13] $end +$var wire 8 F# \[14] $end +$var wire 8 G# \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 H# value $end +$var string 1 I# range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 J# config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 K# \$tag $end +$scope struct HdlSome $end +$var wire 64 L# start_pc $end +$var wire 8 M# fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 N# \[0] $end +$var wire 8 O# \[1] $end +$var wire 8 P# \[2] $end +$var wire 8 Q# \[3] $end +$var wire 8 R# \[4] $end +$var wire 8 S# \[5] $end +$var wire 8 T# \[6] $end +$var wire 8 U# \[7] $end +$var wire 8 V# \[8] $end +$var wire 8 W# \[9] $end +$var wire 8 X# \[10] $end +$var wire 8 Y# \[11] $end +$var wire 8 Z# \[12] $end +$var wire 8 [# \[13] $end +$var wire 8 \# \[14] $end +$var wire 8 ]# \[15] $end +$upscope $end +$scope struct error $end +$var string 1 ^# \$tag $end +$var string 1 _# HdlSome $end +$upscope $end +$var string 1 `# config $end +$upscope $end +$upscope $end +$var wire 1 a# ready $end +$upscope $end +$scope struct cancel $end +$var string 1 b# \$tag $end +$scope struct HdlSome $end +$var wire 5 c# value $end +$var string 1 d# range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct i_cache $end +$scope struct \[0] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 e# \[0] $end +$var reg 8 f# \[1] $end +$var reg 8 g# \[2] $end +$var reg 8 h# \[3] $end +$var reg 8 i# \[4] $end +$var reg 8 j# \[5] $end +$var reg 8 k# \[6] $end +$var reg 8 l# \[7] $end +$var reg 8 m# \[8] $end +$var reg 8 n# \[9] $end +$var reg 8 o# \[10] $end +$var reg 8 p# \[11] $end +$var reg 8 q# \[12] $end +$var reg 8 r# \[13] $end +$var reg 8 s# \[14] $end +$var reg 8 t# \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 u# \[0] $end +$var reg 8 v# \[1] $end +$var reg 8 w# \[2] $end +$var reg 8 x# \[3] $end +$var reg 8 y# \[4] $end +$var reg 8 z# \[5] $end +$var reg 8 {# \[6] $end +$var reg 8 |# \[7] $end +$var reg 8 }# \[8] $end +$var reg 8 ~# \[9] $end +$var reg 8 !$ \[10] $end +$var reg 8 "$ \[11] $end +$var reg 8 #$ \[12] $end +$var reg 8 $$ \[13] $end +$var reg 8 %$ \[14] $end +$var reg 8 &$ \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 '$ \[0] $end +$var reg 8 ($ \[1] $end +$var reg 8 )$ \[2] $end +$var reg 8 *$ \[3] $end +$var reg 8 +$ \[4] $end +$var reg 8 ,$ \[5] $end +$var reg 8 -$ \[6] $end +$var reg 8 .$ \[7] $end +$var reg 8 /$ \[8] $end +$var reg 8 0$ \[9] $end +$var reg 8 1$ \[10] $end +$var reg 8 2$ \[11] $end +$var reg 8 3$ \[12] $end +$var reg 8 4$ \[13] $end +$var reg 8 5$ \[14] $end +$var reg 8 6$ \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 7$ \[0] $end +$var reg 8 8$ \[1] $end +$var reg 8 9$ \[2] $end +$var reg 8 :$ \[3] $end +$var reg 8 ;$ \[4] $end +$var reg 8 <$ \[5] $end +$var reg 8 =$ \[6] $end +$var reg 8 >$ \[7] $end +$var reg 8 ?$ \[8] $end +$var reg 8 @$ \[9] $end +$var reg 8 A$ \[10] $end +$var reg 8 B$ \[11] $end +$var reg 8 C$ \[12] $end +$var reg 8 D$ \[13] $end +$var reg 8 E$ \[14] $end +$var reg 8 F$ \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 G$ \$tag $end +$var reg 54 H$ HdlSome $end +$upscope $end +$var string 1 I$ config $end +$upscope $end +$scope struct \[1] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 J$ \[0] $end +$var reg 8 K$ \[1] $end +$var reg 8 L$ \[2] $end +$var reg 8 M$ \[3] $end +$var reg 8 N$ \[4] $end +$var reg 8 O$ \[5] $end +$var reg 8 P$ \[6] $end +$var reg 8 Q$ \[7] $end +$var reg 8 R$ \[8] $end +$var reg 8 S$ \[9] $end +$var reg 8 T$ \[10] $end +$var reg 8 U$ \[11] $end +$var reg 8 V$ \[12] $end +$var reg 8 W$ \[13] $end +$var reg 8 X$ \[14] $end +$var reg 8 Y$ \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 Z$ \[0] $end +$var reg 8 [$ \[1] $end +$var reg 8 \$ \[2] $end +$var reg 8 ]$ \[3] $end +$var reg 8 ^$ \[4] $end +$var reg 8 _$ \[5] $end +$var reg 8 `$ \[6] $end +$var reg 8 a$ \[7] $end +$var reg 8 b$ \[8] $end +$var reg 8 c$ \[9] $end +$var reg 8 d$ \[10] $end +$var reg 8 e$ \[11] $end +$var reg 8 f$ \[12] $end +$var reg 8 g$ \[13] $end +$var reg 8 h$ \[14] $end +$var reg 8 i$ \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 j$ \[0] $end +$var reg 8 k$ \[1] $end +$var reg 8 l$ \[2] $end +$var reg 8 m$ \[3] $end +$var reg 8 n$ \[4] $end +$var reg 8 o$ \[5] $end +$var reg 8 p$ \[6] $end +$var reg 8 q$ \[7] $end +$var reg 8 r$ \[8] $end +$var reg 8 s$ \[9] $end +$var reg 8 t$ \[10] $end +$var reg 8 u$ \[11] $end +$var reg 8 v$ \[12] $end +$var reg 8 w$ \[13] $end +$var reg 8 x$ \[14] $end +$var reg 8 y$ \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 z$ \[0] $end +$var reg 8 {$ \[1] $end +$var reg 8 |$ \[2] $end +$var reg 8 }$ \[3] $end +$var reg 8 ~$ \[4] $end +$var reg 8 !% \[5] $end +$var reg 8 "% \[6] $end +$var reg 8 #% \[7] $end +$var reg 8 $% \[8] $end +$var reg 8 %% \[9] $end +$var reg 8 &% \[10] $end +$var reg 8 '% \[11] $end +$var reg 8 (% \[12] $end +$var reg 8 )% \[13] $end +$var reg 8 *% \[14] $end +$var reg 8 +% \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ,% \$tag $end +$var reg 54 -% HdlSome $end +$upscope $end +$var string 1 .% config $end +$upscope $end +$scope struct \[2] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 /% \[0] $end +$var reg 8 0% \[1] $end +$var reg 8 1% \[2] $end +$var reg 8 2% \[3] $end +$var reg 8 3% \[4] $end +$var reg 8 4% \[5] $end +$var reg 8 5% \[6] $end +$var reg 8 6% \[7] $end +$var reg 8 7% \[8] $end +$var reg 8 8% \[9] $end +$var reg 8 9% \[10] $end +$var reg 8 :% \[11] $end +$var reg 8 ;% \[12] $end +$var reg 8 <% \[13] $end +$var reg 8 =% \[14] $end +$var reg 8 >% \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 ?% \[0] $end +$var reg 8 @% \[1] $end +$var reg 8 A% \[2] $end +$var reg 8 B% \[3] $end +$var reg 8 C% \[4] $end +$var reg 8 D% \[5] $end +$var reg 8 E% \[6] $end +$var reg 8 F% \[7] $end +$var reg 8 G% \[8] $end +$var reg 8 H% \[9] $end +$var reg 8 I% \[10] $end +$var reg 8 J% \[11] $end +$var reg 8 K% \[12] $end +$var reg 8 L% \[13] $end +$var reg 8 M% \[14] $end +$var reg 8 N% \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 O% \[0] $end +$var reg 8 P% \[1] $end +$var reg 8 Q% \[2] $end +$var reg 8 R% \[3] $end +$var reg 8 S% \[4] $end +$var reg 8 T% \[5] $end +$var reg 8 U% \[6] $end +$var reg 8 V% \[7] $end +$var reg 8 W% \[8] $end +$var reg 8 X% \[9] $end +$var reg 8 Y% \[10] $end +$var reg 8 Z% \[11] $end +$var reg 8 [% \[12] $end +$var reg 8 \% \[13] $end +$var reg 8 ]% \[14] $end +$var reg 8 ^% \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 _% \[0] $end +$var reg 8 `% \[1] $end +$var reg 8 a% \[2] $end +$var reg 8 b% \[3] $end +$var reg 8 c% \[4] $end +$var reg 8 d% \[5] $end +$var reg 8 e% \[6] $end +$var reg 8 f% \[7] $end +$var reg 8 g% \[8] $end +$var reg 8 h% \[9] $end +$var reg 8 i% \[10] $end +$var reg 8 j% \[11] $end +$var reg 8 k% \[12] $end +$var reg 8 l% \[13] $end +$var reg 8 m% \[14] $end +$var reg 8 n% \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 o% \$tag $end +$var reg 54 p% HdlSome $end +$upscope $end +$var string 1 q% config $end +$upscope $end +$scope struct \[3] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 r% \[0] $end +$var reg 8 s% \[1] $end +$var reg 8 t% \[2] $end +$var reg 8 u% \[3] $end +$var reg 8 v% \[4] $end +$var reg 8 w% \[5] $end +$var reg 8 x% \[6] $end +$var reg 8 y% \[7] $end +$var reg 8 z% \[8] $end +$var reg 8 {% \[9] $end +$var reg 8 |% \[10] $end +$var reg 8 }% \[11] $end +$var reg 8 ~% \[12] $end +$var reg 8 !& \[13] $end +$var reg 8 "& \[14] $end +$var reg 8 #& \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 $& \[0] $end +$var reg 8 %& \[1] $end +$var reg 8 && \[2] $end +$var reg 8 '& \[3] $end +$var reg 8 (& \[4] $end +$var reg 8 )& \[5] $end +$var reg 8 *& \[6] $end +$var reg 8 +& \[7] $end +$var reg 8 ,& \[8] $end +$var reg 8 -& \[9] $end +$var reg 8 .& \[10] $end +$var reg 8 /& \[11] $end +$var reg 8 0& \[12] $end +$var reg 8 1& \[13] $end +$var reg 8 2& \[14] $end +$var reg 8 3& \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 4& \[0] $end +$var reg 8 5& \[1] $end +$var reg 8 6& \[2] $end +$var reg 8 7& \[3] $end +$var reg 8 8& \[4] $end +$var reg 8 9& \[5] $end +$var reg 8 :& \[6] $end +$var reg 8 ;& \[7] $end +$var reg 8 <& \[8] $end +$var reg 8 =& \[9] $end +$var reg 8 >& \[10] $end +$var reg 8 ?& \[11] $end +$var reg 8 @& \[12] $end +$var reg 8 A& \[13] $end +$var reg 8 B& \[14] $end +$var reg 8 C& \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 D& \[0] $end +$var reg 8 E& \[1] $end +$var reg 8 F& \[2] $end +$var reg 8 G& \[3] $end +$var reg 8 H& \[4] $end +$var reg 8 I& \[5] $end +$var reg 8 J& \[6] $end +$var reg 8 K& \[7] $end +$var reg 8 L& \[8] $end +$var reg 8 M& \[9] $end +$var reg 8 N& \[10] $end +$var reg 8 O& \[11] $end +$var reg 8 P& \[12] $end +$var reg 8 Q& \[13] $end +$var reg 8 R& \[14] $end +$var reg 8 S& \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 T& \$tag $end +$var reg 54 U& HdlSome $end +$upscope $end +$var string 1 V& config $end +$upscope $end +$scope struct \[4] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 W& \[0] $end +$var reg 8 X& \[1] $end +$var reg 8 Y& \[2] $end +$var reg 8 Z& \[3] $end +$var reg 8 [& \[4] $end +$var reg 8 \& \[5] $end +$var reg 8 ]& \[6] $end +$var reg 8 ^& \[7] $end +$var reg 8 _& \[8] $end +$var reg 8 `& \[9] $end +$var reg 8 a& \[10] $end +$var reg 8 b& \[11] $end +$var reg 8 c& \[12] $end +$var reg 8 d& \[13] $end +$var reg 8 e& \[14] $end +$var reg 8 f& \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 g& \[0] $end +$var reg 8 h& \[1] $end +$var reg 8 i& \[2] $end +$var reg 8 j& \[3] $end +$var reg 8 k& \[4] $end +$var reg 8 l& \[5] $end +$var reg 8 m& \[6] $end +$var reg 8 n& \[7] $end +$var reg 8 o& \[8] $end +$var reg 8 p& \[9] $end +$var reg 8 q& \[10] $end +$var reg 8 r& \[11] $end +$var reg 8 s& \[12] $end +$var reg 8 t& \[13] $end +$var reg 8 u& \[14] $end +$var reg 8 v& \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 w& \[0] $end +$var reg 8 x& \[1] $end +$var reg 8 y& \[2] $end +$var reg 8 z& \[3] $end +$var reg 8 {& \[4] $end +$var reg 8 |& \[5] $end +$var reg 8 }& \[6] $end +$var reg 8 ~& \[7] $end +$var reg 8 !' \[8] $end +$var reg 8 "' \[9] $end +$var reg 8 #' \[10] $end +$var reg 8 $' \[11] $end +$var reg 8 %' \[12] $end +$var reg 8 &' \[13] $end +$var reg 8 '' \[14] $end +$var reg 8 (' \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 )' \[0] $end +$var reg 8 *' \[1] $end +$var reg 8 +' \[2] $end +$var reg 8 ,' \[3] $end +$var reg 8 -' \[4] $end +$var reg 8 .' \[5] $end +$var reg 8 /' \[6] $end +$var reg 8 0' \[7] $end +$var reg 8 1' \[8] $end +$var reg 8 2' \[9] $end +$var reg 8 3' \[10] $end +$var reg 8 4' \[11] $end +$var reg 8 5' \[12] $end +$var reg 8 6' \[13] $end +$var reg 8 7' \[14] $end +$var reg 8 8' \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 9' \$tag $end +$var reg 54 :' HdlSome $end +$upscope $end +$var string 1 ;' config $end +$upscope $end +$scope struct \[5] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 <' \[0] $end +$var reg 8 =' \[1] $end +$var reg 8 >' \[2] $end +$var reg 8 ?' \[3] $end +$var reg 8 @' \[4] $end +$var reg 8 A' \[5] $end +$var reg 8 B' \[6] $end +$var reg 8 C' \[7] $end +$var reg 8 D' \[8] $end +$var reg 8 E' \[9] $end +$var reg 8 F' \[10] $end +$var reg 8 G' \[11] $end +$var reg 8 H' \[12] $end +$var reg 8 I' \[13] $end +$var reg 8 J' \[14] $end +$var reg 8 K' \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 L' \[0] $end +$var reg 8 M' \[1] $end +$var reg 8 N' \[2] $end +$var reg 8 O' \[3] $end +$var reg 8 P' \[4] $end +$var reg 8 Q' \[5] $end +$var reg 8 R' \[6] $end +$var reg 8 S' \[7] $end +$var reg 8 T' \[8] $end +$var reg 8 U' \[9] $end +$var reg 8 V' \[10] $end +$var reg 8 W' \[11] $end +$var reg 8 X' \[12] $end +$var reg 8 Y' \[13] $end +$var reg 8 Z' \[14] $end +$var reg 8 [' \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 \' \[0] $end +$var reg 8 ]' \[1] $end +$var reg 8 ^' \[2] $end +$var reg 8 _' \[3] $end +$var reg 8 `' \[4] $end +$var reg 8 a' \[5] $end +$var reg 8 b' \[6] $end +$var reg 8 c' \[7] $end +$var reg 8 d' \[8] $end +$var reg 8 e' \[9] $end +$var reg 8 f' \[10] $end +$var reg 8 g' \[11] $end +$var reg 8 h' \[12] $end +$var reg 8 i' \[13] $end +$var reg 8 j' \[14] $end +$var reg 8 k' \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 l' \[0] $end +$var reg 8 m' \[1] $end +$var reg 8 n' \[2] $end +$var reg 8 o' \[3] $end +$var reg 8 p' \[4] $end +$var reg 8 q' \[5] $end +$var reg 8 r' \[6] $end +$var reg 8 s' \[7] $end +$var reg 8 t' \[8] $end +$var reg 8 u' \[9] $end +$var reg 8 v' \[10] $end +$var reg 8 w' \[11] $end +$var reg 8 x' \[12] $end +$var reg 8 y' \[13] $end +$var reg 8 z' \[14] $end +$var reg 8 {' \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 |' \$tag $end +$var reg 54 }' HdlSome $end +$upscope $end +$var string 1 ~' config $end +$upscope $end +$scope struct \[6] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 !( \[0] $end +$var reg 8 "( \[1] $end +$var reg 8 #( \[2] $end +$var reg 8 $( \[3] $end +$var reg 8 %( \[4] $end +$var reg 8 &( \[5] $end +$var reg 8 '( \[6] $end +$var reg 8 (( \[7] $end +$var reg 8 )( \[8] $end +$var reg 8 *( \[9] $end +$var reg 8 +( \[10] $end +$var reg 8 ,( \[11] $end +$var reg 8 -( \[12] $end +$var reg 8 .( \[13] $end +$var reg 8 /( \[14] $end +$var reg 8 0( \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 1( \[0] $end +$var reg 8 2( \[1] $end +$var reg 8 3( \[2] $end +$var reg 8 4( \[3] $end +$var reg 8 5( \[4] $end +$var reg 8 6( \[5] $end +$var reg 8 7( \[6] $end +$var reg 8 8( \[7] $end +$var reg 8 9( \[8] $end +$var reg 8 :( \[9] $end +$var reg 8 ;( \[10] $end +$var reg 8 <( \[11] $end +$var reg 8 =( \[12] $end +$var reg 8 >( \[13] $end +$var reg 8 ?( \[14] $end +$var reg 8 @( \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 A( \[0] $end +$var reg 8 B( \[1] $end +$var reg 8 C( \[2] $end +$var reg 8 D( \[3] $end +$var reg 8 E( \[4] $end +$var reg 8 F( \[5] $end +$var reg 8 G( \[6] $end +$var reg 8 H( \[7] $end +$var reg 8 I( \[8] $end +$var reg 8 J( \[9] $end +$var reg 8 K( \[10] $end +$var reg 8 L( \[11] $end +$var reg 8 M( \[12] $end +$var reg 8 N( \[13] $end +$var reg 8 O( \[14] $end +$var reg 8 P( \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 Q( \[0] $end +$var reg 8 R( \[1] $end +$var reg 8 S( \[2] $end +$var reg 8 T( \[3] $end +$var reg 8 U( \[4] $end +$var reg 8 V( \[5] $end +$var reg 8 W( \[6] $end +$var reg 8 X( \[7] $end +$var reg 8 Y( \[8] $end +$var reg 8 Z( \[9] $end +$var reg 8 [( \[10] $end +$var reg 8 \( \[11] $end +$var reg 8 ]( \[12] $end +$var reg 8 ^( \[13] $end +$var reg 8 _( \[14] $end +$var reg 8 `( \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 a( \$tag $end +$var reg 54 b( HdlSome $end +$upscope $end +$var string 1 c( config $end +$upscope $end +$scope struct \[7] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 d( \[0] $end +$var reg 8 e( \[1] $end +$var reg 8 f( \[2] $end +$var reg 8 g( \[3] $end +$var reg 8 h( \[4] $end +$var reg 8 i( \[5] $end +$var reg 8 j( \[6] $end +$var reg 8 k( \[7] $end +$var reg 8 l( \[8] $end +$var reg 8 m( \[9] $end +$var reg 8 n( \[10] $end +$var reg 8 o( \[11] $end +$var reg 8 p( \[12] $end +$var reg 8 q( \[13] $end +$var reg 8 r( \[14] $end +$var reg 8 s( \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 t( \[0] $end +$var reg 8 u( \[1] $end +$var reg 8 v( \[2] $end +$var reg 8 w( \[3] $end +$var reg 8 x( \[4] $end +$var reg 8 y( \[5] $end +$var reg 8 z( \[6] $end +$var reg 8 {( \[7] $end +$var reg 8 |( \[8] $end +$var reg 8 }( \[9] $end +$var reg 8 ~( \[10] $end +$var reg 8 !) \[11] $end +$var reg 8 ") \[12] $end +$var reg 8 #) \[13] $end +$var reg 8 $) \[14] $end +$var reg 8 %) \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 &) \[0] $end +$var reg 8 ') \[1] $end +$var reg 8 () \[2] $end +$var reg 8 )) \[3] $end +$var reg 8 *) \[4] $end +$var reg 8 +) \[5] $end +$var reg 8 ,) \[6] $end +$var reg 8 -) \[7] $end +$var reg 8 .) \[8] $end +$var reg 8 /) \[9] $end +$var reg 8 0) \[10] $end +$var reg 8 1) \[11] $end +$var reg 8 2) \[12] $end +$var reg 8 3) \[13] $end +$var reg 8 4) \[14] $end +$var reg 8 5) \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 6) \[0] $end +$var reg 8 7) \[1] $end +$var reg 8 8) \[2] $end +$var reg 8 9) \[3] $end +$var reg 8 :) \[4] $end +$var reg 8 ;) \[5] $end +$var reg 8 <) \[6] $end +$var reg 8 =) \[7] $end +$var reg 8 >) \[8] $end +$var reg 8 ?) \[9] $end +$var reg 8 @) \[10] $end +$var reg 8 A) \[11] $end +$var reg 8 B) \[12] $end +$var reg 8 C) \[13] $end +$var reg 8 D) \[14] $end +$var reg 8 E) \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 F) \$tag $end +$var reg 54 G) HdlSome $end +$upscope $end +$var string 1 H) config $end +$upscope $end +$scope struct \[8] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 I) \[0] $end +$var reg 8 J) \[1] $end +$var reg 8 K) \[2] $end +$var reg 8 L) \[3] $end +$var reg 8 M) \[4] $end +$var reg 8 N) \[5] $end +$var reg 8 O) \[6] $end +$var reg 8 P) \[7] $end +$var reg 8 Q) \[8] $end +$var reg 8 R) \[9] $end +$var reg 8 S) \[10] $end +$var reg 8 T) \[11] $end +$var reg 8 U) \[12] $end +$var reg 8 V) \[13] $end +$var reg 8 W) \[14] $end +$var reg 8 X) \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 Y) \[0] $end +$var reg 8 Z) \[1] $end +$var reg 8 [) \[2] $end +$var reg 8 \) \[3] $end +$var reg 8 ]) \[4] $end +$var reg 8 ^) \[5] $end +$var reg 8 _) \[6] $end +$var reg 8 `) \[7] $end +$var reg 8 a) \[8] $end +$var reg 8 b) \[9] $end +$var reg 8 c) \[10] $end +$var reg 8 d) \[11] $end +$var reg 8 e) \[12] $end +$var reg 8 f) \[13] $end +$var reg 8 g) \[14] $end +$var reg 8 h) \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 i) \[0] $end +$var reg 8 j) \[1] $end +$var reg 8 k) \[2] $end +$var reg 8 l) \[3] $end +$var reg 8 m) \[4] $end +$var reg 8 n) \[5] $end +$var reg 8 o) \[6] $end +$var reg 8 p) \[7] $end +$var reg 8 q) \[8] $end +$var reg 8 r) \[9] $end +$var reg 8 s) \[10] $end +$var reg 8 t) \[11] $end +$var reg 8 u) \[12] $end +$var reg 8 v) \[13] $end +$var reg 8 w) \[14] $end +$var reg 8 x) \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 y) \[0] $end +$var reg 8 z) \[1] $end +$var reg 8 {) \[2] $end +$var reg 8 |) \[3] $end +$var reg 8 }) \[4] $end +$var reg 8 ~) \[5] $end +$var reg 8 !* \[6] $end +$var reg 8 "* \[7] $end +$var reg 8 #* \[8] $end +$var reg 8 $* \[9] $end +$var reg 8 %* \[10] $end +$var reg 8 &* \[11] $end +$var reg 8 '* \[12] $end +$var reg 8 (* \[13] $end +$var reg 8 )* \[14] $end +$var reg 8 ** \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 +* \$tag $end +$var reg 54 ,* HdlSome $end +$upscope $end +$var string 1 -* config $end +$upscope $end +$scope struct \[9] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 .* \[0] $end +$var reg 8 /* \[1] $end +$var reg 8 0* \[2] $end +$var reg 8 1* \[3] $end +$var reg 8 2* \[4] $end +$var reg 8 3* \[5] $end +$var reg 8 4* \[6] $end +$var reg 8 5* \[7] $end +$var reg 8 6* \[8] $end +$var reg 8 7* \[9] $end +$var reg 8 8* \[10] $end +$var reg 8 9* \[11] $end +$var reg 8 :* \[12] $end +$var reg 8 ;* \[13] $end +$var reg 8 <* \[14] $end +$var reg 8 =* \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 >* \[0] $end +$var reg 8 ?* \[1] $end +$var reg 8 @* \[2] $end +$var reg 8 A* \[3] $end +$var reg 8 B* \[4] $end +$var reg 8 C* \[5] $end +$var reg 8 D* \[6] $end +$var reg 8 E* \[7] $end +$var reg 8 F* \[8] $end +$var reg 8 G* \[9] $end +$var reg 8 H* \[10] $end +$var reg 8 I* \[11] $end +$var reg 8 J* \[12] $end +$var reg 8 K* \[13] $end +$var reg 8 L* \[14] $end +$var reg 8 M* \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 N* \[0] $end +$var reg 8 O* \[1] $end +$var reg 8 P* \[2] $end +$var reg 8 Q* \[3] $end +$var reg 8 R* \[4] $end +$var reg 8 S* \[5] $end +$var reg 8 T* \[6] $end +$var reg 8 U* \[7] $end +$var reg 8 V* \[8] $end +$var reg 8 W* \[9] $end +$var reg 8 X* \[10] $end +$var reg 8 Y* \[11] $end +$var reg 8 Z* \[12] $end +$var reg 8 [* \[13] $end +$var reg 8 \* \[14] $end +$var reg 8 ]* \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 ^* \[0] $end +$var reg 8 _* \[1] $end +$var reg 8 `* \[2] $end +$var reg 8 a* \[3] $end +$var reg 8 b* \[4] $end +$var reg 8 c* \[5] $end +$var reg 8 d* \[6] $end +$var reg 8 e* \[7] $end +$var reg 8 f* \[8] $end +$var reg 8 g* \[9] $end +$var reg 8 h* \[10] $end +$var reg 8 i* \[11] $end +$var reg 8 j* \[12] $end +$var reg 8 k* \[13] $end +$var reg 8 l* \[14] $end +$var reg 8 m* \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 n* \$tag $end +$var reg 54 o* HdlSome $end +$upscope $end +$var string 1 p* config $end +$upscope $end +$scope struct \[10] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 q* \[0] $end +$var reg 8 r* \[1] $end +$var reg 8 s* \[2] $end +$var reg 8 t* \[3] $end +$var reg 8 u* \[4] $end +$var reg 8 v* \[5] $end +$var reg 8 w* \[6] $end +$var reg 8 x* \[7] $end +$var reg 8 y* \[8] $end +$var reg 8 z* \[9] $end +$var reg 8 {* \[10] $end +$var reg 8 |* \[11] $end +$var reg 8 }* \[12] $end +$var reg 8 ~* \[13] $end +$var reg 8 !+ \[14] $end +$var reg 8 "+ \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 #+ \[0] $end +$var reg 8 $+ \[1] $end +$var reg 8 %+ \[2] $end +$var reg 8 &+ \[3] $end +$var reg 8 '+ \[4] $end +$var reg 8 (+ \[5] $end +$var reg 8 )+ \[6] $end +$var reg 8 *+ \[7] $end +$var reg 8 ++ \[8] $end +$var reg 8 ,+ \[9] $end +$var reg 8 -+ \[10] $end +$var reg 8 .+ \[11] $end +$var reg 8 /+ \[12] $end +$var reg 8 0+ \[13] $end +$var reg 8 1+ \[14] $end +$var reg 8 2+ \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 3+ \[0] $end +$var reg 8 4+ \[1] $end +$var reg 8 5+ \[2] $end +$var reg 8 6+ \[3] $end +$var reg 8 7+ \[4] $end +$var reg 8 8+ \[5] $end +$var reg 8 9+ \[6] $end +$var reg 8 :+ \[7] $end +$var reg 8 ;+ \[8] $end +$var reg 8 <+ \[9] $end +$var reg 8 =+ \[10] $end +$var reg 8 >+ \[11] $end +$var reg 8 ?+ \[12] $end +$var reg 8 @+ \[13] $end +$var reg 8 A+ \[14] $end +$var reg 8 B+ \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C+ \[0] $end +$var reg 8 D+ \[1] $end +$var reg 8 E+ \[2] $end +$var reg 8 F+ \[3] $end +$var reg 8 G+ \[4] $end +$var reg 8 H+ \[5] $end +$var reg 8 I+ \[6] $end +$var reg 8 J+ \[7] $end +$var reg 8 K+ \[8] $end +$var reg 8 L+ \[9] $end +$var reg 8 M+ \[10] $end +$var reg 8 N+ \[11] $end +$var reg 8 O+ \[12] $end +$var reg 8 P+ \[13] $end +$var reg 8 Q+ \[14] $end +$var reg 8 R+ \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 S+ \$tag $end +$var reg 54 T+ HdlSome $end +$upscope $end +$var string 1 U+ config $end +$upscope $end +$scope struct \[11] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 V+ \[0] $end +$var reg 8 W+ \[1] $end +$var reg 8 X+ \[2] $end +$var reg 8 Y+ \[3] $end +$var reg 8 Z+ \[4] $end +$var reg 8 [+ \[5] $end +$var reg 8 \+ \[6] $end +$var reg 8 ]+ \[7] $end +$var reg 8 ^+ \[8] $end +$var reg 8 _+ \[9] $end +$var reg 8 `+ \[10] $end +$var reg 8 a+ \[11] $end +$var reg 8 b+ \[12] $end +$var reg 8 c+ \[13] $end +$var reg 8 d+ \[14] $end +$var reg 8 e+ \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 f+ \[0] $end +$var reg 8 g+ \[1] $end +$var reg 8 h+ \[2] $end +$var reg 8 i+ \[3] $end +$var reg 8 j+ \[4] $end +$var reg 8 k+ \[5] $end +$var reg 8 l+ \[6] $end +$var reg 8 m+ \[7] $end +$var reg 8 n+ \[8] $end +$var reg 8 o+ \[9] $end +$var reg 8 p+ \[10] $end +$var reg 8 q+ \[11] $end +$var reg 8 r+ \[12] $end +$var reg 8 s+ \[13] $end +$var reg 8 t+ \[14] $end +$var reg 8 u+ \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 v+ \[0] $end +$var reg 8 w+ \[1] $end +$var reg 8 x+ \[2] $end +$var reg 8 y+ \[3] $end +$var reg 8 z+ \[4] $end +$var reg 8 {+ \[5] $end +$var reg 8 |+ \[6] $end +$var reg 8 }+ \[7] $end +$var reg 8 ~+ \[8] $end +$var reg 8 !, \[9] $end +$var reg 8 ", \[10] $end +$var reg 8 #, \[11] $end +$var reg 8 $, \[12] $end +$var reg 8 %, \[13] $end +$var reg 8 &, \[14] $end +$var reg 8 ', \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 (, \[0] $end +$var reg 8 ), \[1] $end +$var reg 8 *, \[2] $end +$var reg 8 +, \[3] $end +$var reg 8 ,, \[4] $end +$var reg 8 -, \[5] $end +$var reg 8 ., \[6] $end +$var reg 8 /, \[7] $end +$var reg 8 0, \[8] $end +$var reg 8 1, \[9] $end +$var reg 8 2, \[10] $end +$var reg 8 3, \[11] $end +$var reg 8 4, \[12] $end +$var reg 8 5, \[13] $end +$var reg 8 6, \[14] $end +$var reg 8 7, \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 8, \$tag $end +$var reg 54 9, HdlSome $end +$upscope $end +$var string 1 :, config $end +$upscope $end +$scope struct \[12] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ;, \[0] $end +$var reg 8 <, \[1] $end +$var reg 8 =, \[2] $end +$var reg 8 >, \[3] $end +$var reg 8 ?, \[4] $end +$var reg 8 @, \[5] $end +$var reg 8 A, \[6] $end +$var reg 8 B, \[7] $end +$var reg 8 C, \[8] $end +$var reg 8 D, \[9] $end +$var reg 8 E, \[10] $end +$var reg 8 F, \[11] $end +$var reg 8 G, \[12] $end +$var reg 8 H, \[13] $end +$var reg 8 I, \[14] $end +$var reg 8 J, \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 K, \[0] $end +$var reg 8 L, \[1] $end +$var reg 8 M, \[2] $end +$var reg 8 N, \[3] $end +$var reg 8 O, \[4] $end +$var reg 8 P, \[5] $end +$var reg 8 Q, \[6] $end +$var reg 8 R, \[7] $end +$var reg 8 S, \[8] $end +$var reg 8 T, \[9] $end +$var reg 8 U, \[10] $end +$var reg 8 V, \[11] $end +$var reg 8 W, \[12] $end +$var reg 8 X, \[13] $end +$var reg 8 Y, \[14] $end +$var reg 8 Z, \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 [, \[0] $end +$var reg 8 \, \[1] $end +$var reg 8 ], \[2] $end +$var reg 8 ^, \[3] $end +$var reg 8 _, \[4] $end +$var reg 8 `, \[5] $end +$var reg 8 a, \[6] $end +$var reg 8 b, \[7] $end +$var reg 8 c, \[8] $end +$var reg 8 d, \[9] $end +$var reg 8 e, \[10] $end +$var reg 8 f, \[11] $end +$var reg 8 g, \[12] $end +$var reg 8 h, \[13] $end +$var reg 8 i, \[14] $end +$var reg 8 j, \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 k, \[0] $end +$var reg 8 l, \[1] $end +$var reg 8 m, \[2] $end +$var reg 8 n, \[3] $end +$var reg 8 o, \[4] $end +$var reg 8 p, \[5] $end +$var reg 8 q, \[6] $end +$var reg 8 r, \[7] $end +$var reg 8 s, \[8] $end +$var reg 8 t, \[9] $end +$var reg 8 u, \[10] $end +$var reg 8 v, \[11] $end +$var reg 8 w, \[12] $end +$var reg 8 x, \[13] $end +$var reg 8 y, \[14] $end +$var reg 8 z, \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 {, \$tag $end +$var reg 54 |, HdlSome $end +$upscope $end +$var string 1 }, config $end +$upscope $end +$scope struct \[13] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ~, \[0] $end +$var reg 8 !- \[1] $end +$var reg 8 "- \[2] $end +$var reg 8 #- \[3] $end +$var reg 8 $- \[4] $end +$var reg 8 %- \[5] $end +$var reg 8 &- \[6] $end +$var reg 8 '- \[7] $end +$var reg 8 (- \[8] $end +$var reg 8 )- \[9] $end +$var reg 8 *- \[10] $end +$var reg 8 +- \[11] $end +$var reg 8 ,- \[12] $end +$var reg 8 -- \[13] $end +$var reg 8 .- \[14] $end +$var reg 8 /- \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 0- \[0] $end +$var reg 8 1- \[1] $end +$var reg 8 2- \[2] $end +$var reg 8 3- \[3] $end +$var reg 8 4- \[4] $end +$var reg 8 5- \[5] $end +$var reg 8 6- \[6] $end +$var reg 8 7- \[7] $end +$var reg 8 8- \[8] $end +$var reg 8 9- \[9] $end +$var reg 8 :- \[10] $end +$var reg 8 ;- \[11] $end +$var reg 8 <- \[12] $end +$var reg 8 =- \[13] $end +$var reg 8 >- \[14] $end +$var reg 8 ?- \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 @- \[0] $end +$var reg 8 A- \[1] $end +$var reg 8 B- \[2] $end +$var reg 8 C- \[3] $end +$var reg 8 D- \[4] $end +$var reg 8 E- \[5] $end +$var reg 8 F- \[6] $end +$var reg 8 G- \[7] $end +$var reg 8 H- \[8] $end +$var reg 8 I- \[9] $end +$var reg 8 J- \[10] $end +$var reg 8 K- \[11] $end +$var reg 8 L- \[12] $end +$var reg 8 M- \[13] $end +$var reg 8 N- \[14] $end +$var reg 8 O- \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 P- \[0] $end +$var reg 8 Q- \[1] $end +$var reg 8 R- \[2] $end +$var reg 8 S- \[3] $end +$var reg 8 T- \[4] $end +$var reg 8 U- \[5] $end +$var reg 8 V- \[6] $end +$var reg 8 W- \[7] $end +$var reg 8 X- \[8] $end +$var reg 8 Y- \[9] $end +$var reg 8 Z- \[10] $end +$var reg 8 [- \[11] $end +$var reg 8 \- \[12] $end +$var reg 8 ]- \[13] $end +$var reg 8 ^- \[14] $end +$var reg 8 _- \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 `- \$tag $end +$var reg 54 a- HdlSome $end +$upscope $end +$var string 1 b- config $end +$upscope $end +$scope struct \[14] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 c- \[0] $end +$var reg 8 d- \[1] $end +$var reg 8 e- \[2] $end +$var reg 8 f- \[3] $end +$var reg 8 g- \[4] $end +$var reg 8 h- \[5] $end +$var reg 8 i- \[6] $end +$var reg 8 j- \[7] $end +$var reg 8 k- \[8] $end +$var reg 8 l- \[9] $end +$var reg 8 m- \[10] $end +$var reg 8 n- \[11] $end +$var reg 8 o- \[12] $end +$var reg 8 p- \[13] $end +$var reg 8 q- \[14] $end +$var reg 8 r- \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 s- \[0] $end +$var reg 8 t- \[1] $end +$var reg 8 u- \[2] $end +$var reg 8 v- \[3] $end +$var reg 8 w- \[4] $end +$var reg 8 x- \[5] $end +$var reg 8 y- \[6] $end +$var reg 8 z- \[7] $end +$var reg 8 {- \[8] $end +$var reg 8 |- \[9] $end +$var reg 8 }- \[10] $end +$var reg 8 ~- \[11] $end +$var reg 8 !. \[12] $end +$var reg 8 ". \[13] $end +$var reg 8 #. \[14] $end +$var reg 8 $. \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 %. \[0] $end +$var reg 8 &. \[1] $end +$var reg 8 '. \[2] $end +$var reg 8 (. \[3] $end +$var reg 8 ). \[4] $end +$var reg 8 *. \[5] $end +$var reg 8 +. \[6] $end +$var reg 8 ,. \[7] $end +$var reg 8 -. \[8] $end +$var reg 8 .. \[9] $end +$var reg 8 /. \[10] $end +$var reg 8 0. \[11] $end +$var reg 8 1. \[12] $end +$var reg 8 2. \[13] $end +$var reg 8 3. \[14] $end +$var reg 8 4. \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 5. \[0] $end +$var reg 8 6. \[1] $end +$var reg 8 7. \[2] $end +$var reg 8 8. \[3] $end +$var reg 8 9. \[4] $end +$var reg 8 :. \[5] $end +$var reg 8 ;. \[6] $end +$var reg 8 <. \[7] $end +$var reg 8 =. \[8] $end +$var reg 8 >. \[9] $end +$var reg 8 ?. \[10] $end +$var reg 8 @. \[11] $end +$var reg 8 A. \[12] $end +$var reg 8 B. \[13] $end +$var reg 8 C. \[14] $end +$var reg 8 D. \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 E. \$tag $end +$var reg 54 F. HdlSome $end +$upscope $end +$var string 1 G. config $end +$upscope $end +$scope struct \[15] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 H. \[0] $end +$var reg 8 I. \[1] $end +$var reg 8 J. \[2] $end +$var reg 8 K. \[3] $end +$var reg 8 L. \[4] $end +$var reg 8 M. \[5] $end +$var reg 8 N. \[6] $end +$var reg 8 O. \[7] $end +$var reg 8 P. \[8] $end +$var reg 8 Q. \[9] $end +$var reg 8 R. \[10] $end +$var reg 8 S. \[11] $end +$var reg 8 T. \[12] $end +$var reg 8 U. \[13] $end +$var reg 8 V. \[14] $end +$var reg 8 W. \[15] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 X. \[0] $end +$var reg 8 Y. \[1] $end +$var reg 8 Z. \[2] $end +$var reg 8 [. \[3] $end +$var reg 8 \. \[4] $end +$var reg 8 ]. \[5] $end +$var reg 8 ^. \[6] $end +$var reg 8 _. \[7] $end +$var reg 8 `. \[8] $end +$var reg 8 a. \[9] $end +$var reg 8 b. \[10] $end +$var reg 8 c. \[11] $end +$var reg 8 d. \[12] $end +$var reg 8 e. \[13] $end +$var reg 8 f. \[14] $end +$var reg 8 g. \[15] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 h. \[0] $end +$var reg 8 i. \[1] $end +$var reg 8 j. \[2] $end +$var reg 8 k. \[3] $end +$var reg 8 l. \[4] $end +$var reg 8 m. \[5] $end +$var reg 8 n. \[6] $end +$var reg 8 o. \[7] $end +$var reg 8 p. \[8] $end +$var reg 8 q. \[9] $end +$var reg 8 r. \[10] $end +$var reg 8 s. \[11] $end +$var reg 8 t. \[12] $end +$var reg 8 u. \[13] $end +$var reg 8 v. \[14] $end +$var reg 8 w. \[15] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 x. \[0] $end +$var reg 8 y. \[1] $end +$var reg 8 z. \[2] $end +$var reg 8 {. \[3] $end +$var reg 8 |. \[4] $end +$var reg 8 }. \[5] $end +$var reg 8 ~. \[6] $end +$var reg 8 !/ \[7] $end +$var reg 8 "/ \[8] $end +$var reg 8 #/ \[9] $end +$var reg 8 $/ \[10] $end +$var reg 8 %/ \[11] $end +$var reg 8 &/ \[12] $end +$var reg 8 '/ \[13] $end +$var reg 8 (/ \[14] $end +$var reg 8 )/ \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 */ \$tag $end +$var reg 54 +/ HdlSome $end +$upscope $end +$var string 1 ,/ config $end +$upscope $end +$upscope $end +$scope struct l1_i_cache_impl $end +$scope struct cd $end +$var wire 1 ^7 clk $end +$var wire 1 _7 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 `7 \$tag $end +$scope struct HdlSome $end +$var string 1 a7 kind $end +$var wire 64 b7 addr $end +$scope struct write_data $end +$var wire 8 c7 \[0] $end +$var wire 8 d7 \[1] $end +$var wire 8 e7 \[2] $end +$var wire 8 f7 \[3] $end +$var wire 8 g7 \[4] $end +$var wire 8 h7 \[5] $end +$var wire 8 i7 \[6] $end +$var wire 8 j7 \[7] $end +$var wire 8 k7 \[8] $end +$var wire 8 l7 \[9] $end +$var wire 8 m7 \[10] $end +$var wire 8 n7 \[11] $end +$var wire 8 o7 \[12] $end +$var wire 8 p7 \[13] $end +$var wire 8 q7 \[14] $end +$var wire 8 r7 \[15] $end +$upscope $end +$var string 1 s7 config $end +$upscope $end +$upscope $end +$var wire 1 t7 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 u7 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 v7 \$tag $end +$var string 1 w7 Success $end +$var string 1 x7 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 y7 \[0] $end +$var wire 8 z7 \[1] $end +$var wire 8 {7 \[2] $end +$var wire 8 |7 \[3] $end +$var wire 8 }7 \[4] $end +$var wire 8 ~7 \[5] $end +$var wire 8 !8 \[6] $end +$var wire 8 "8 \[7] $end +$var wire 8 #8 \[8] $end +$var wire 8 $8 \[9] $end +$var wire 8 %8 \[10] $end +$var wire 8 &8 \[11] $end +$var wire 8 '8 \[12] $end +$var wire 8 (8 \[13] $end +$var wire 8 )8 \[14] $end +$var wire 8 *8 \[15] $end +$upscope $end +$var string 1 +8 config $end +$upscope $end +$upscope $end +$var wire 1 ,8 ready $end +$upscope $end +$var string 1 -8 config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 .8 \$tag $end +$scope struct HdlSome $end +$var wire 64 /8 start_pc $end +$var wire 8 08 fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 18 ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 28 \$tag $end +$scope struct HdlSome $end +$var wire 5 38 value $end +$var string 1 48 range $end +$upscope $end +$upscope $end +$var wire 1 58 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 68 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 78 \[0] $end +$var wire 8 88 \[1] $end +$var wire 8 98 \[2] $end +$var wire 8 :8 \[3] $end +$var wire 8 ;8 \[4] $end +$var wire 8 <8 \[5] $end +$var wire 8 =8 \[6] $end +$var wire 8 >8 \[7] $end +$var wire 8 ?8 \[8] $end +$var wire 8 @8 \[9] $end +$var wire 8 A8 \[10] $end +$var wire 8 B8 \[11] $end +$var wire 8 C8 \[12] $end +$var wire 8 D8 \[13] $end +$var wire 8 E8 \[14] $end +$var wire 8 F8 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 G8 value $end +$var string 1 H8 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 I8 config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 J8 \$tag $end +$scope struct HdlSome $end +$var wire 64 K8 start_pc $end +$var wire 8 L8 fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 M8 \[0] $end +$var wire 8 N8 \[1] $end +$var wire 8 O8 \[2] $end +$var wire 8 P8 \[3] $end +$var wire 8 Q8 \[4] $end +$var wire 8 R8 \[5] $end +$var wire 8 S8 \[6] $end +$var wire 8 T8 \[7] $end +$var wire 8 U8 \[8] $end +$var wire 8 V8 \[9] $end +$var wire 8 W8 \[10] $end +$var wire 8 X8 \[11] $end +$var wire 8 Y8 \[12] $end +$var wire 8 Z8 \[13] $end +$var wire 8 [8 \[14] $end +$var wire 8 \8 \[15] $end +$upscope $end +$scope struct error $end +$var string 1 ]8 \$tag $end +$var string 1 ^8 HdlSome $end +$upscope $end +$var string 1 _8 config $end +$upscope $end +$upscope $end +$var wire 1 `8 ready $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 a8 value $end +$var string 1 b8 range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 c8 addr $end +$var wire 1 d8 en $end +$var wire 1 e8 clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 f8 \[0] $end +$var wire 8 g8 \[1] $end +$var wire 8 h8 \[2] $end +$var wire 8 i8 \[3] $end +$var wire 8 j8 \[4] $end +$var wire 8 k8 \[5] $end +$var wire 8 l8 \[6] $end +$var wire 8 m8 \[7] $end +$var wire 8 n8 \[8] $end +$var wire 8 o8 \[9] $end +$var wire 8 p8 \[10] $end +$var wire 8 q8 \[11] $end +$var wire 8 r8 \[12] $end +$var wire 8 s8 \[13] $end +$var wire 8 t8 \[14] $end +$var wire 8 u8 \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 v8 \[0] $end +$var wire 8 w8 \[1] $end +$var wire 8 x8 \[2] $end +$var wire 8 y8 \[3] $end +$var wire 8 z8 \[4] $end +$var wire 8 {8 \[5] $end +$var wire 8 |8 \[6] $end +$var wire 8 }8 \[7] $end +$var wire 8 ~8 \[8] $end +$var wire 8 !9 \[9] $end +$var wire 8 "9 \[10] $end +$var wire 8 #9 \[11] $end +$var wire 8 $9 \[12] $end +$var wire 8 %9 \[13] $end +$var wire 8 &9 \[14] $end +$var wire 8 '9 \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 (9 \[0] $end +$var wire 8 )9 \[1] $end +$var wire 8 *9 \[2] $end +$var wire 8 +9 \[3] $end +$var wire 8 ,9 \[4] $end +$var wire 8 -9 \[5] $end +$var wire 8 .9 \[6] $end +$var wire 8 /9 \[7] $end +$var wire 8 09 \[8] $end +$var wire 8 19 \[9] $end +$var wire 8 29 \[10] $end +$var wire 8 39 \[11] $end +$var wire 8 49 \[12] $end +$var wire 8 59 \[13] $end +$var wire 8 69 \[14] $end +$var wire 8 79 \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 89 \[0] $end +$var wire 8 99 \[1] $end +$var wire 8 :9 \[2] $end +$var wire 8 ;9 \[3] $end +$var wire 8 <9 \[4] $end +$var wire 8 =9 \[5] $end +$var wire 8 >9 \[6] $end +$var wire 8 ?9 \[7] $end +$var wire 8 @9 \[8] $end +$var wire 8 A9 \[9] $end +$var wire 8 B9 \[10] $end +$var wire 8 C9 \[11] $end +$var wire 8 D9 \[12] $end +$var wire 8 E9 \[13] $end +$var wire 8 F9 \[14] $end +$var wire 8 G9 \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 H9 \$tag $end +$var wire 54 I9 HdlSome $end +$upscope $end +$var string 1 J9 config $end +$upscope $end +$var wire 1 K9 wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 L9 \[0] $end +$var wire 8 M9 \[1] $end +$var wire 8 N9 \[2] $end +$var wire 8 O9 \[3] $end +$var wire 8 P9 \[4] $end +$var wire 8 Q9 \[5] $end +$var wire 8 R9 \[6] $end +$var wire 8 S9 \[7] $end +$var wire 8 T9 \[8] $end +$var wire 8 U9 \[9] $end +$var wire 8 V9 \[10] $end +$var wire 8 W9 \[11] $end +$var wire 8 X9 \[12] $end +$var wire 8 Y9 \[13] $end +$var wire 8 Z9 \[14] $end +$var wire 8 [9 \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 \9 \[0] $end +$var wire 8 ]9 \[1] $end +$var wire 8 ^9 \[2] $end +$var wire 8 _9 \[3] $end +$var wire 8 `9 \[4] $end +$var wire 8 a9 \[5] $end +$var wire 8 b9 \[6] $end +$var wire 8 c9 \[7] $end +$var wire 8 d9 \[8] $end +$var wire 8 e9 \[9] $end +$var wire 8 f9 \[10] $end +$var wire 8 g9 \[11] $end +$var wire 8 h9 \[12] $end +$var wire 8 i9 \[13] $end +$var wire 8 j9 \[14] $end +$var wire 8 k9 \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 l9 \[0] $end +$var wire 8 m9 \[1] $end +$var wire 8 n9 \[2] $end +$var wire 8 o9 \[3] $end +$var wire 8 p9 \[4] $end +$var wire 8 q9 \[5] $end +$var wire 8 r9 \[6] $end +$var wire 8 s9 \[7] $end +$var wire 8 t9 \[8] $end +$var wire 8 u9 \[9] $end +$var wire 8 v9 \[10] $end +$var wire 8 w9 \[11] $end +$var wire 8 x9 \[12] $end +$var wire 8 y9 \[13] $end +$var wire 8 z9 \[14] $end +$var wire 8 {9 \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 |9 \[0] $end +$var wire 8 }9 \[1] $end +$var wire 8 ~9 \[2] $end +$var wire 8 !: \[3] $end +$var wire 8 ": \[4] $end +$var wire 8 #: \[5] $end +$var wire 8 $: \[6] $end +$var wire 8 %: \[7] $end +$var wire 8 &: \[8] $end +$var wire 8 ': \[9] $end +$var wire 8 (: \[10] $end +$var wire 8 ): \[11] $end +$var wire 8 *: \[12] $end +$var wire 8 +: \[13] $end +$var wire 8 ,: \[14] $end +$var wire 8 -: \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 .: \$tag $end +$var wire 54 /: HdlSome $end +$upscope $end +$var string 1 0: config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 1: \[0] $end +$var wire 1 2: \[1] $end +$var wire 1 3: \[2] $end +$var wire 1 4: \[3] $end +$var wire 1 5: \[4] $end +$var wire 1 6: \[5] $end +$var wire 1 7: \[6] $end +$var wire 1 8: \[7] $end +$var wire 1 9: \[8] $end +$var wire 1 :: \[9] $end +$var wire 1 ;: \[10] $end +$var wire 1 <: \[11] $end +$var wire 1 =: \[12] $end +$var wire 1 >: \[13] $end +$var wire 1 ?: \[14] $end +$var wire 1 @: \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 A: \[0] $end +$var wire 1 B: \[1] $end +$var wire 1 C: \[2] $end +$var wire 1 D: \[3] $end +$var wire 1 E: \[4] $end +$var wire 1 F: \[5] $end +$var wire 1 G: \[6] $end +$var wire 1 H: \[7] $end +$var wire 1 I: \[8] $end +$var wire 1 J: \[9] $end +$var wire 1 K: \[10] $end +$var wire 1 L: \[11] $end +$var wire 1 M: \[12] $end +$var wire 1 N: \[13] $end +$var wire 1 O: \[14] $end +$var wire 1 P: \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 Q: \[0] $end +$var wire 1 R: \[1] $end +$var wire 1 S: \[2] $end +$var wire 1 T: \[3] $end +$var wire 1 U: \[4] $end +$var wire 1 V: \[5] $end +$var wire 1 W: \[6] $end +$var wire 1 X: \[7] $end +$var wire 1 Y: \[8] $end +$var wire 1 Z: \[9] $end +$var wire 1 [: \[10] $end +$var wire 1 \: \[11] $end +$var wire 1 ]: \[12] $end +$var wire 1 ^: \[13] $end +$var wire 1 _: \[14] $end +$var wire 1 `: \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 a: \[0] $end +$var wire 1 b: \[1] $end +$var wire 1 c: \[2] $end +$var wire 1 d: \[3] $end +$var wire 1 e: \[4] $end +$var wire 1 f: \[5] $end +$var wire 1 g: \[6] $end +$var wire 1 h: \[7] $end +$var wire 1 i: \[8] $end +$var wire 1 j: \[9] $end +$var wire 1 k: \[10] $end +$var wire 1 l: \[11] $end +$var wire 1 m: \[12] $end +$var wire 1 n: \[13] $end +$var wire 1 o: \[14] $end +$var wire 1 p: \[15] $end +$upscope $end +$upscope $end +$var wire 1 q: addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 r: start_pc $end +$var wire 8 s: fetch_block_id $end +$var string 1 t: state $end +$var wire 1 u: canceled $end +$scope struct error $end +$var string 1 v: \$tag $end +$var string 1 w: HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 x: \$tag $end +$scope struct HdlSome $end +$var wire 2 y: value $end +$var string 1 z: range $end +$upscope $end +$upscope $end +$var string 1 {: config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 |: \$tag $end +$scope struct HdlSome $end +$var wire 2 }: value $end +$var string 1 ~: range $end +$upscope $end +$upscope $end +$var string 1 !; config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 "; \[0] $end +$var wire 8 #; \[1] $end +$var wire 8 $; \[2] $end +$var wire 8 %; \[3] $end +$var wire 8 &; \[4] $end +$var wire 8 '; \[5] $end +$var wire 8 (; \[6] $end +$var wire 8 ); \[7] $end +$var wire 8 *; \[8] $end +$var wire 8 +; \[9] $end +$var wire 8 ,; \[10] $end +$var wire 8 -; \[11] $end +$var wire 8 .; \[12] $end +$var wire 8 /; \[13] $end +$var wire 8 0; \[14] $end +$var wire 8 1; \[15] $end +$upscope $end +$var string 1 2; config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 3; start_pc $end +$var wire 8 4; fetch_block_id $end +$var string 1 5; state $end +$var wire 1 6; canceled $end +$scope struct error $end +$var string 1 7; \$tag $end +$var string 1 8; HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 9; \$tag $end +$scope struct HdlSome $end +$var wire 2 :; value $end +$var string 1 ;; range $end +$upscope $end +$upscope $end +$var string 1 <; config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 =; \$tag $end +$scope struct HdlSome $end +$var wire 2 >; value $end +$var string 1 ?; range $end +$upscope $end +$upscope $end +$var string 1 @; config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 A; \[0] $end +$var wire 8 B; \[1] $end +$var wire 8 C; \[2] $end +$var wire 8 D; \[3] $end +$var wire 8 E; \[4] $end +$var wire 8 F; \[5] $end +$var wire 8 G; \[6] $end +$var wire 8 H; \[7] $end +$var wire 8 I; \[8] $end +$var wire 8 J; \[9] $end +$var wire 8 K; \[10] $end +$var wire 8 L; \[11] $end +$var wire 8 M; \[12] $end +$var wire 8 N; \[13] $end +$var wire 8 O; \[14] $end +$var wire 8 P; \[15] $end +$upscope $end +$var string 1 Q; config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 R; start_pc $end +$var wire 8 S; fetch_block_id $end +$var string 1 T; state $end +$var wire 1 U; canceled $end +$scope struct error $end +$var string 1 V; \$tag $end +$var string 1 W; HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 X; \$tag $end +$scope struct HdlSome $end +$var wire 2 Y; value $end +$var string 1 Z; range $end +$upscope $end +$upscope $end +$var string 1 [; config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 \; \$tag $end +$scope struct HdlSome $end +$var wire 2 ]; value $end +$var string 1 ^; range $end +$upscope $end +$upscope $end +$var string 1 _; config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 `; \[0] $end +$var wire 8 a; \[1] $end +$var wire 8 b; \[2] $end +$var wire 8 c; \[3] $end +$var wire 8 d; \[4] $end +$var wire 8 e; \[5] $end +$var wire 8 f; \[6] $end +$var wire 8 g; \[7] $end +$var wire 8 h; \[8] $end +$var wire 8 i; \[9] $end +$var wire 8 j; \[10] $end +$var wire 8 k; \[11] $end +$var wire 8 l; \[12] $end +$var wire 8 m; \[13] $end +$var wire 8 n; \[14] $end +$var wire 8 o; \[15] $end +$upscope $end +$var string 1 p; config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 q; start_pc $end +$var wire 8 r; fetch_block_id $end +$var string 1 s; state $end +$var wire 1 t; canceled $end +$scope struct error $end +$var string 1 u; \$tag $end +$var string 1 v; HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 w; \$tag $end +$scope struct HdlSome $end +$var wire 2 x; value $end +$var string 1 y; range $end +$upscope $end +$upscope $end +$var string 1 z; config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 {; \$tag $end +$scope struct HdlSome $end +$var wire 2 |; value $end +$var string 1 }; range $end +$upscope $end +$upscope $end +$var string 1 ~; config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 !< \[0] $end +$var wire 8 "< \[1] $end +$var wire 8 #< \[2] $end +$var wire 8 $< \[3] $end +$var wire 8 %< \[4] $end +$var wire 8 &< \[5] $end +$var wire 8 '< \[6] $end +$var wire 8 (< \[7] $end +$var wire 8 )< \[8] $end +$var wire 8 *< \[9] $end +$var wire 8 +< \[10] $end +$var wire 8 ,< \[11] $end +$var wire 8 -< \[12] $end +$var wire 8 .< \[13] $end +$var wire 8 /< \[14] $end +$var wire 8 0< \[15] $end +$upscope $end +$var string 1 1< config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 2< start_pc $end +$var wire 8 3< fetch_block_id $end +$var string 1 4< state $end +$var wire 1 5< canceled $end +$scope struct error $end +$var string 1 6< \$tag $end +$var string 1 7< HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 8< \$tag $end +$scope struct HdlSome $end +$var wire 2 9< value $end +$var string 1 :< range $end +$upscope $end +$upscope $end +$var string 1 ;< config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 << \$tag $end +$scope struct HdlSome $end +$var wire 2 =< value $end +$var string 1 >< range $end +$upscope $end +$upscope $end +$var string 1 ?< config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 @< \[0] $end +$var wire 8 A< \[1] $end +$var wire 8 B< \[2] $end +$var wire 8 C< \[3] $end +$var wire 8 D< \[4] $end +$var wire 8 E< \[5] $end +$var wire 8 F< \[6] $end +$var wire 8 G< \[7] $end +$var wire 8 H< \[8] $end +$var wire 8 I< \[9] $end +$var wire 8 J< \[10] $end +$var wire 8 K< \[11] $end +$var wire 8 L< \[12] $end +$var wire 8 M< \[13] $end +$var wire 8 N< \[14] $end +$var wire 8 O< \[15] $end +$upscope $end +$var string 1 P< config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 Q< start_pc $end +$var wire 8 R< fetch_block_id $end +$var string 1 S< state $end +$var wire 1 T< canceled $end +$scope struct error $end +$var string 1 U< \$tag $end +$var string 1 V< HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 W< \$tag $end +$scope struct HdlSome $end +$var wire 2 X< value $end +$var string 1 Y< range $end +$upscope $end +$upscope $end +$var string 1 Z< config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 [< \$tag $end +$scope struct HdlSome $end +$var wire 2 \< value $end +$var string 1 ]< range $end +$upscope $end +$upscope $end +$var string 1 ^< config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 _< \[0] $end +$var wire 8 `< \[1] $end +$var wire 8 a< \[2] $end +$var wire 8 b< \[3] $end +$var wire 8 c< \[4] $end +$var wire 8 d< \[5] $end +$var wire 8 e< \[6] $end +$var wire 8 f< \[7] $end +$var wire 8 g< \[8] $end +$var wire 8 h< \[9] $end +$var wire 8 i< \[10] $end +$var wire 8 j< \[11] $end +$var wire 8 k< \[12] $end +$var wire 8 l< \[13] $end +$var wire 8 m< \[14] $end +$var wire 8 n< \[15] $end +$upscope $end +$var string 1 o< config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 p< start_pc $end +$var wire 8 q< fetch_block_id $end +$var string 1 r< state $end +$var wire 1 s< canceled $end +$scope struct error $end +$var string 1 t< \$tag $end +$var string 1 u< HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 v< \$tag $end +$scope struct HdlSome $end +$var wire 2 w< value $end +$var string 1 x< range $end +$upscope $end +$upscope $end +$var string 1 y< config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 z< \$tag $end +$scope struct HdlSome $end +$var wire 2 {< value $end +$var string 1 |< range $end +$upscope $end +$upscope $end +$var string 1 }< config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ~< \[0] $end +$var wire 8 != \[1] $end +$var wire 8 "= \[2] $end +$var wire 8 #= \[3] $end +$var wire 8 $= \[4] $end +$var wire 8 %= \[5] $end +$var wire 8 &= \[6] $end +$var wire 8 '= \[7] $end +$var wire 8 (= \[8] $end +$var wire 8 )= \[9] $end +$var wire 8 *= \[10] $end +$var wire 8 += \[11] $end +$var wire 8 ,= \[12] $end +$var wire 8 -= \[13] $end +$var wire 8 .= \[14] $end +$var wire 8 /= \[15] $end +$upscope $end +$var string 1 0= config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 1= start_pc $end +$var wire 8 2= fetch_block_id $end +$var string 1 3= state $end +$var wire 1 4= canceled $end +$scope struct error $end +$var string 1 5= \$tag $end +$var string 1 6= HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 7= \$tag $end +$scope struct HdlSome $end +$var wire 2 8= value $end +$var string 1 9= range $end +$upscope $end +$upscope $end +$var string 1 := config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 ;= \$tag $end +$scope struct HdlSome $end +$var wire 2 <= value $end +$var string 1 == range $end +$upscope $end +$upscope $end +$var string 1 >= config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ?= \[0] $end +$var wire 8 @= \[1] $end +$var wire 8 A= \[2] $end +$var wire 8 B= \[3] $end +$var wire 8 C= \[4] $end +$var wire 8 D= \[5] $end +$var wire 8 E= \[6] $end +$var wire 8 F= \[7] $end +$var wire 8 G= \[8] $end +$var wire 8 H= \[9] $end +$var wire 8 I= \[10] $end +$var wire 8 J= \[11] $end +$var wire 8 K= \[12] $end +$var wire 8 L= \[13] $end +$var wire 8 M= \[14] $end +$var wire 8 N= \[15] $end +$upscope $end +$var string 1 O= config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 P= start_pc $end +$var wire 8 Q= fetch_block_id $end +$var string 1 R= state $end +$var wire 1 S= canceled $end +$scope struct error $end +$var string 1 T= \$tag $end +$var string 1 U= HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 V= \$tag $end +$scope struct HdlSome $end +$var wire 2 W= value $end +$var string 1 X= range $end +$upscope $end +$upscope $end +$var string 1 Y= config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 Z= \$tag $end +$scope struct HdlSome $end +$var wire 2 [= value $end +$var string 1 \= range $end +$upscope $end +$upscope $end +$var string 1 ]= config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ^= \[0] $end +$var wire 8 _= \[1] $end +$var wire 8 `= \[2] $end +$var wire 8 a= \[3] $end +$var wire 8 b= \[4] $end +$var wire 8 c= \[5] $end +$var wire 8 d= \[6] $end +$var wire 8 e= \[7] $end +$var wire 8 f= \[8] $end +$var wire 8 g= \[9] $end +$var wire 8 h= \[10] $end +$var wire 8 i= \[11] $end +$var wire 8 j= \[12] $end +$var wire 8 k= \[13] $end +$var wire 8 l= \[14] $end +$var wire 8 m= \[15] $end +$upscope $end +$var string 1 n= config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 o= start_pc $end +$var wire 8 p= fetch_block_id $end +$var string 1 q= state $end +$var wire 1 r= canceled $end +$scope struct error $end +$var string 1 s= \$tag $end +$var string 1 t= HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 u= \$tag $end +$scope struct HdlSome $end +$var wire 2 v= value $end +$var string 1 w= range $end +$upscope $end +$upscope $end +$var string 1 x= config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 y= \$tag $end +$scope struct HdlSome $end +$var wire 2 z= value $end +$var string 1 {= range $end +$upscope $end +$upscope $end +$var string 1 |= config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 }= \[0] $end +$var wire 8 ~= \[1] $end +$var wire 8 !> \[2] $end +$var wire 8 "> \[3] $end +$var wire 8 #> \[4] $end +$var wire 8 $> \[5] $end +$var wire 8 %> \[6] $end +$var wire 8 &> \[7] $end +$var wire 8 '> \[8] $end +$var wire 8 (> \[9] $end +$var wire 8 )> \[10] $end +$var wire 8 *> \[11] $end +$var wire 8 +> \[12] $end +$var wire 8 ,> \[13] $end +$var wire 8 -> \[14] $end +$var wire 8 .> \[15] $end +$upscope $end +$var string 1 /> config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 0> start_pc $end +$var wire 8 1> fetch_block_id $end +$var string 1 2> state $end +$var wire 1 3> canceled $end +$scope struct error $end +$var string 1 4> \$tag $end +$var string 1 5> HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 6> \$tag $end +$scope struct HdlSome $end +$var wire 2 7> value $end +$var string 1 8> range $end +$upscope $end +$upscope $end +$var string 1 9> config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 :> \$tag $end +$scope struct HdlSome $end +$var wire 2 ;> value $end +$var string 1 <> range $end +$upscope $end +$upscope $end +$var string 1 => config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 >> \[0] $end +$var wire 8 ?> \[1] $end +$var wire 8 @> \[2] $end +$var wire 8 A> \[3] $end +$var wire 8 B> \[4] $end +$var wire 8 C> \[5] $end +$var wire 8 D> \[6] $end +$var wire 8 E> \[7] $end +$var wire 8 F> \[8] $end +$var wire 8 G> \[9] $end +$var wire 8 H> \[10] $end +$var wire 8 I> \[11] $end +$var wire 8 J> \[12] $end +$var wire 8 K> \[13] $end +$var wire 8 L> \[14] $end +$var wire 8 M> \[15] $end +$upscope $end +$var string 1 N> config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 O> start_pc $end +$var wire 8 P> fetch_block_id $end +$var string 1 Q> state $end +$var wire 1 R> canceled $end +$scope struct error $end +$var string 1 S> \$tag $end +$var string 1 T> HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 U> \$tag $end +$scope struct HdlSome $end +$var wire 2 V> value $end +$var string 1 W> range $end +$upscope $end +$upscope $end +$var string 1 X> config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 Y> \$tag $end +$scope struct HdlSome $end +$var wire 2 Z> value $end +$var string 1 [> range $end +$upscope $end +$upscope $end +$var string 1 \> config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ]> \[0] $end +$var wire 8 ^> \[1] $end +$var wire 8 _> \[2] $end +$var wire 8 `> \[3] $end +$var wire 8 a> \[4] $end +$var wire 8 b> \[5] $end +$var wire 8 c> \[6] $end +$var wire 8 d> \[7] $end +$var wire 8 e> \[8] $end +$var wire 8 f> \[9] $end +$var wire 8 g> \[10] $end +$var wire 8 h> \[11] $end +$var wire 8 i> \[12] $end +$var wire 8 j> \[13] $end +$var wire 8 k> \[14] $end +$var wire 8 l> \[15] $end +$upscope $end +$var string 1 m> config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 n> start_pc $end +$var wire 8 o> fetch_block_id $end +$var string 1 p> state $end +$var wire 1 q> canceled $end +$scope struct error $end +$var string 1 r> \$tag $end +$var string 1 s> HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 t> \$tag $end +$scope struct HdlSome $end +$var wire 2 u> value $end +$var string 1 v> range $end +$upscope $end +$upscope $end +$var string 1 w> config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 x> \$tag $end +$scope struct HdlSome $end +$var wire 2 y> value $end +$var string 1 z> range $end +$upscope $end +$upscope $end +$var string 1 {> config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 |> \[0] $end +$var wire 8 }> \[1] $end +$var wire 8 ~> \[2] $end +$var wire 8 !? \[3] $end +$var wire 8 "? \[4] $end +$var wire 8 #? \[5] $end +$var wire 8 $? \[6] $end +$var wire 8 %? \[7] $end +$var wire 8 &? \[8] $end +$var wire 8 '? \[9] $end +$var wire 8 (? \[10] $end +$var wire 8 )? \[11] $end +$var wire 8 *? \[12] $end +$var wire 8 +? \[13] $end +$var wire 8 ,? \[14] $end +$var wire 8 -? \[15] $end +$upscope $end +$var string 1 .? config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 /? start_pc $end +$var wire 8 0? fetch_block_id $end +$var string 1 1? state $end +$var wire 1 2? canceled $end +$scope struct error $end +$var string 1 3? \$tag $end +$var string 1 4? HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 5? \$tag $end +$scope struct HdlSome $end +$var wire 2 6? value $end +$var string 1 7? range $end +$upscope $end +$upscope $end +$var string 1 8? config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 9? \$tag $end +$scope struct HdlSome $end +$var wire 2 :? value $end +$var string 1 ;? range $end +$upscope $end +$upscope $end +$var string 1 ? \[1] $end +$var wire 8 ?? \[2] $end +$var wire 8 @? \[3] $end +$var wire 8 A? \[4] $end +$var wire 8 B? \[5] $end +$var wire 8 C? \[6] $end +$var wire 8 D? \[7] $end +$var wire 8 E? \[8] $end +$var wire 8 F? \[9] $end +$var wire 8 G? \[10] $end +$var wire 8 H? \[11] $end +$var wire 8 I? \[12] $end +$var wire 8 J? \[13] $end +$var wire 8 K? \[14] $end +$var wire 8 L? \[15] $end +$upscope $end +$var string 1 M? config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 N? start_pc $end +$var wire 8 O? fetch_block_id $end +$var string 1 P? state $end +$var wire 1 Q? canceled $end +$scope struct error $end +$var string 1 R? \$tag $end +$var string 1 S? HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 T? \$tag $end +$scope struct HdlSome $end +$var wire 2 U? value $end +$var string 1 V? range $end +$upscope $end +$upscope $end +$var string 1 W? config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 X? \$tag $end +$scope struct HdlSome $end +$var wire 2 Y? value $end +$var string 1 Z? range $end +$upscope $end +$upscope $end +$var string 1 [? config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 \? \[0] $end +$var wire 8 ]? \[1] $end +$var wire 8 ^? \[2] $end +$var wire 8 _? \[3] $end +$var wire 8 `? \[4] $end +$var wire 8 a? \[5] $end +$var wire 8 b? \[6] $end +$var wire 8 c? \[7] $end +$var wire 8 d? \[8] $end +$var wire 8 e? \[9] $end +$var wire 8 f? \[10] $end +$var wire 8 g? \[11] $end +$var wire 8 h? \[12] $end +$var wire 8 i? \[13] $end +$var wire 8 j? \[14] $end +$var wire 8 k? \[15] $end +$upscope $end +$var string 1 l? config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 m? start_pc $end +$var wire 8 n? fetch_block_id $end +$var string 1 o? state $end +$var wire 1 p? canceled $end +$scope struct error $end +$var string 1 q? \$tag $end +$var string 1 r? HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 s? \$tag $end +$scope struct HdlSome $end +$var wire 2 t? value $end +$var string 1 u? range $end +$upscope $end +$upscope $end +$var string 1 v? config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 w? \$tag $end +$scope struct HdlSome $end +$var wire 2 x? value $end +$var string 1 y? range $end +$upscope $end +$upscope $end +$var string 1 z? config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 {? \[0] $end +$var wire 8 |? \[1] $end +$var wire 8 }? \[2] $end +$var wire 8 ~? \[3] $end +$var wire 8 !@ \[4] $end +$var wire 8 "@ \[5] $end +$var wire 8 #@ \[6] $end +$var wire 8 $@ \[7] $end +$var wire 8 %@ \[8] $end +$var wire 8 &@ \[9] $end +$var wire 8 '@ \[10] $end +$var wire 8 (@ \[11] $end +$var wire 8 )@ \[12] $end +$var wire 8 *@ \[13] $end +$var wire 8 +@ \[14] $end +$var wire 8 ,@ \[15] $end +$upscope $end +$var string 1 -@ config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 .@ value $end +$var string 1 /@ range $end +$upscope $end +$upscope $end +$var string 1 0@ config $end +$upscope $end +$upscope $end +$scope module l1_i_cache_impl_2 $end +$scope struct cd $end +$var wire 1 -/ clk $end +$var wire 1 ./ rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 // \$tag $end +$scope struct HdlSome $end +$var string 1 0/ kind $end +$var wire 64 1/ addr $end +$scope struct write_data $end +$var wire 8 2/ \[0] $end +$var wire 8 3/ \[1] $end +$var wire 8 4/ \[2] $end +$var wire 8 5/ \[3] $end +$var wire 8 6/ \[4] $end +$var wire 8 7/ \[5] $end +$var wire 8 8/ \[6] $end +$var wire 8 9/ \[7] $end +$var wire 8 :/ \[8] $end +$var wire 8 ;/ \[9] $end +$var wire 8 / \[12] $end +$var wire 8 ?/ \[13] $end +$var wire 8 @/ \[14] $end +$var wire 8 A/ \[15] $end +$upscope $end +$var string 1 B/ config $end +$upscope $end +$upscope $end +$var wire 1 C/ ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 D/ \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 E/ \$tag $end +$var string 1 F/ Success $end +$var string 1 G/ Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 H/ \[0] $end +$var wire 8 I/ \[1] $end +$var wire 8 J/ \[2] $end +$var wire 8 K/ \[3] $end +$var wire 8 L/ \[4] $end +$var wire 8 M/ \[5] $end +$var wire 8 N/ \[6] $end +$var wire 8 O/ \[7] $end +$var wire 8 P/ \[8] $end +$var wire 8 Q/ \[9] $end +$var wire 8 R/ \[10] $end +$var wire 8 S/ \[11] $end +$var wire 8 T/ \[12] $end +$var wire 8 U/ \[13] $end +$var wire 8 V/ \[14] $end +$var wire 8 W/ \[15] $end +$upscope $end +$var string 1 X/ config $end +$upscope $end +$upscope $end +$var wire 1 Y/ ready $end +$upscope $end +$var string 1 Z/ config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 [/ \$tag $end +$scope struct HdlSome $end +$var wire 64 \/ start_pc $end +$var wire 8 ]/ fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 ^/ ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 _/ \$tag $end +$scope struct HdlSome $end +$var wire 5 `/ value $end +$var string 1 a/ range $end +$upscope $end +$upscope $end +$var wire 1 b/ ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 c/ \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 d/ \[0] $end +$var wire 8 e/ \[1] $end +$var wire 8 f/ \[2] $end +$var wire 8 g/ \[3] $end +$var wire 8 h/ \[4] $end +$var wire 8 i/ \[5] $end +$var wire 8 j/ \[6] $end +$var wire 8 k/ \[7] $end +$var wire 8 l/ \[8] $end +$var wire 8 m/ \[9] $end +$var wire 8 n/ \[10] $end +$var wire 8 o/ \[11] $end +$var wire 8 p/ \[12] $end +$var wire 8 q/ \[13] $end +$var wire 8 r/ \[14] $end +$var wire 8 s/ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 t/ value $end +$var string 1 u/ range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 v/ config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 w/ \$tag $end +$scope struct HdlSome $end +$var wire 64 x/ start_pc $end +$var wire 8 y/ fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 z/ \[0] $end +$var wire 8 {/ \[1] $end +$var wire 8 |/ \[2] $end +$var wire 8 }/ \[3] $end +$var wire 8 ~/ \[4] $end +$var wire 8 !0 \[5] $end +$var wire 8 "0 \[6] $end +$var wire 8 #0 \[7] $end +$var wire 8 $0 \[8] $end +$var wire 8 %0 \[9] $end +$var wire 8 &0 \[10] $end +$var wire 8 '0 \[11] $end +$var wire 8 (0 \[12] $end +$var wire 8 )0 \[13] $end +$var wire 8 *0 \[14] $end +$var wire 8 +0 \[15] $end +$upscope $end +$scope struct error $end +$var string 1 ,0 \$tag $end +$var string 1 -0 HdlSome $end +$upscope $end +$var string 1 .0 config $end +$upscope $end +$upscope $end +$var wire 1 /0 ready $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 00 value $end +$var string 1 10 range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 20 addr $end +$var wire 1 30 en $end +$var wire 1 40 clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 50 \[0] $end +$var wire 8 60 \[1] $end +$var wire 8 70 \[2] $end +$var wire 8 80 \[3] $end +$var wire 8 90 \[4] $end +$var wire 8 :0 \[5] $end +$var wire 8 ;0 \[6] $end +$var wire 8 <0 \[7] $end +$var wire 8 =0 \[8] $end +$var wire 8 >0 \[9] $end +$var wire 8 ?0 \[10] $end +$var wire 8 @0 \[11] $end +$var wire 8 A0 \[12] $end +$var wire 8 B0 \[13] $end +$var wire 8 C0 \[14] $end +$var wire 8 D0 \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 E0 \[0] $end +$var wire 8 F0 \[1] $end +$var wire 8 G0 \[2] $end +$var wire 8 H0 \[3] $end +$var wire 8 I0 \[4] $end +$var wire 8 J0 \[5] $end +$var wire 8 K0 \[6] $end +$var wire 8 L0 \[7] $end +$var wire 8 M0 \[8] $end +$var wire 8 N0 \[9] $end +$var wire 8 O0 \[10] $end +$var wire 8 P0 \[11] $end +$var wire 8 Q0 \[12] $end +$var wire 8 R0 \[13] $end +$var wire 8 S0 \[14] $end +$var wire 8 T0 \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 U0 \[0] $end +$var wire 8 V0 \[1] $end +$var wire 8 W0 \[2] $end +$var wire 8 X0 \[3] $end +$var wire 8 Y0 \[4] $end +$var wire 8 Z0 \[5] $end +$var wire 8 [0 \[6] $end +$var wire 8 \0 \[7] $end +$var wire 8 ]0 \[8] $end +$var wire 8 ^0 \[9] $end +$var wire 8 _0 \[10] $end +$var wire 8 `0 \[11] $end +$var wire 8 a0 \[12] $end +$var wire 8 b0 \[13] $end +$var wire 8 c0 \[14] $end +$var wire 8 d0 \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 e0 \[0] $end +$var wire 8 f0 \[1] $end +$var wire 8 g0 \[2] $end +$var wire 8 h0 \[3] $end +$var wire 8 i0 \[4] $end +$var wire 8 j0 \[5] $end +$var wire 8 k0 \[6] $end +$var wire 8 l0 \[7] $end +$var wire 8 m0 \[8] $end +$var wire 8 n0 \[9] $end +$var wire 8 o0 \[10] $end +$var wire 8 p0 \[11] $end +$var wire 8 q0 \[12] $end +$var wire 8 r0 \[13] $end +$var wire 8 s0 \[14] $end +$var wire 8 t0 \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 u0 \$tag $end +$var wire 54 v0 HdlSome $end +$upscope $end +$var string 1 w0 config $end +$upscope $end +$var wire 1 x0 wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 y0 \[0] $end +$var wire 8 z0 \[1] $end +$var wire 8 {0 \[2] $end +$var wire 8 |0 \[3] $end +$var wire 8 }0 \[4] $end +$var wire 8 ~0 \[5] $end +$var wire 8 !1 \[6] $end +$var wire 8 "1 \[7] $end +$var wire 8 #1 \[8] $end +$var wire 8 $1 \[9] $end +$var wire 8 %1 \[10] $end +$var wire 8 &1 \[11] $end +$var wire 8 '1 \[12] $end +$var wire 8 (1 \[13] $end +$var wire 8 )1 \[14] $end +$var wire 8 *1 \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 +1 \[0] $end +$var wire 8 ,1 \[1] $end +$var wire 8 -1 \[2] $end +$var wire 8 .1 \[3] $end +$var wire 8 /1 \[4] $end +$var wire 8 01 \[5] $end +$var wire 8 11 \[6] $end +$var wire 8 21 \[7] $end +$var wire 8 31 \[8] $end +$var wire 8 41 \[9] $end +$var wire 8 51 \[10] $end +$var wire 8 61 \[11] $end +$var wire 8 71 \[12] $end +$var wire 8 81 \[13] $end +$var wire 8 91 \[14] $end +$var wire 8 :1 \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 ;1 \[0] $end +$var wire 8 <1 \[1] $end +$var wire 8 =1 \[2] $end +$var wire 8 >1 \[3] $end +$var wire 8 ?1 \[4] $end +$var wire 8 @1 \[5] $end +$var wire 8 A1 \[6] $end +$var wire 8 B1 \[7] $end +$var wire 8 C1 \[8] $end +$var wire 8 D1 \[9] $end +$var wire 8 E1 \[10] $end +$var wire 8 F1 \[11] $end +$var wire 8 G1 \[12] $end +$var wire 8 H1 \[13] $end +$var wire 8 I1 \[14] $end +$var wire 8 J1 \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 K1 \[0] $end +$var wire 8 L1 \[1] $end +$var wire 8 M1 \[2] $end +$var wire 8 N1 \[3] $end +$var wire 8 O1 \[4] $end +$var wire 8 P1 \[5] $end +$var wire 8 Q1 \[6] $end +$var wire 8 R1 \[7] $end +$var wire 8 S1 \[8] $end +$var wire 8 T1 \[9] $end +$var wire 8 U1 \[10] $end +$var wire 8 V1 \[11] $end +$var wire 8 W1 \[12] $end +$var wire 8 X1 \[13] $end +$var wire 8 Y1 \[14] $end +$var wire 8 Z1 \[15] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 [1 \$tag $end +$var wire 54 \1 HdlSome $end +$upscope $end +$var string 1 ]1 config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 ^1 \[0] $end +$var wire 1 _1 \[1] $end +$var wire 1 `1 \[2] $end +$var wire 1 a1 \[3] $end +$var wire 1 b1 \[4] $end +$var wire 1 c1 \[5] $end +$var wire 1 d1 \[6] $end +$var wire 1 e1 \[7] $end +$var wire 1 f1 \[8] $end +$var wire 1 g1 \[9] $end +$var wire 1 h1 \[10] $end +$var wire 1 i1 \[11] $end +$var wire 1 j1 \[12] $end +$var wire 1 k1 \[13] $end +$var wire 1 l1 \[14] $end +$var wire 1 m1 \[15] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 n1 \[0] $end +$var wire 1 o1 \[1] $end +$var wire 1 p1 \[2] $end +$var wire 1 q1 \[3] $end +$var wire 1 r1 \[4] $end +$var wire 1 s1 \[5] $end +$var wire 1 t1 \[6] $end +$var wire 1 u1 \[7] $end +$var wire 1 v1 \[8] $end +$var wire 1 w1 \[9] $end +$var wire 1 x1 \[10] $end +$var wire 1 y1 \[11] $end +$var wire 1 z1 \[12] $end +$var wire 1 {1 \[13] $end +$var wire 1 |1 \[14] $end +$var wire 1 }1 \[15] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 ~1 \[0] $end +$var wire 1 !2 \[1] $end +$var wire 1 "2 \[2] $end +$var wire 1 #2 \[3] $end +$var wire 1 $2 \[4] $end +$var wire 1 %2 \[5] $end +$var wire 1 &2 \[6] $end +$var wire 1 '2 \[7] $end +$var wire 1 (2 \[8] $end +$var wire 1 )2 \[9] $end +$var wire 1 *2 \[10] $end +$var wire 1 +2 \[11] $end +$var wire 1 ,2 \[12] $end +$var wire 1 -2 \[13] $end +$var wire 1 .2 \[14] $end +$var wire 1 /2 \[15] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 02 \[0] $end +$var wire 1 12 \[1] $end +$var wire 1 22 \[2] $end +$var wire 1 32 \[3] $end +$var wire 1 42 \[4] $end +$var wire 1 52 \[5] $end +$var wire 1 62 \[6] $end +$var wire 1 72 \[7] $end +$var wire 1 82 \[8] $end +$var wire 1 92 \[9] $end +$var wire 1 :2 \[10] $end +$var wire 1 ;2 \[11] $end +$var wire 1 <2 \[12] $end +$var wire 1 =2 \[13] $end +$var wire 1 >2 \[14] $end +$var wire 1 ?2 \[15] $end +$upscope $end +$upscope $end +$var wire 1 @2 addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 A2 start_pc $end +$var wire 8 B2 fetch_block_id $end +$var string 1 C2 state $end +$var wire 1 D2 canceled $end +$scope struct error $end +$var string 1 E2 \$tag $end +$var string 1 F2 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 G2 \$tag $end +$scope struct HdlSome $end +$var wire 2 H2 value $end +$var string 1 I2 range $end +$upscope $end +$upscope $end +$var string 1 J2 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 K2 \$tag $end +$scope struct HdlSome $end +$var wire 2 L2 value $end +$var string 1 M2 range $end +$upscope $end +$upscope $end +$var string 1 N2 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 O2 \[0] $end +$var wire 8 P2 \[1] $end +$var wire 8 Q2 \[2] $end +$var wire 8 R2 \[3] $end +$var wire 8 S2 \[4] $end +$var wire 8 T2 \[5] $end +$var wire 8 U2 \[6] $end +$var wire 8 V2 \[7] $end +$var wire 8 W2 \[8] $end +$var wire 8 X2 \[9] $end +$var wire 8 Y2 \[10] $end +$var wire 8 Z2 \[11] $end +$var wire 8 [2 \[12] $end +$var wire 8 \2 \[13] $end +$var wire 8 ]2 \[14] $end +$var wire 8 ^2 \[15] $end +$upscope $end +$var string 1 _2 config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 `2 start_pc $end +$var wire 8 a2 fetch_block_id $end +$var string 1 b2 state $end +$var wire 1 c2 canceled $end +$scope struct error $end +$var string 1 d2 \$tag $end +$var string 1 e2 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 f2 \$tag $end +$scope struct HdlSome $end +$var wire 2 g2 value $end +$var string 1 h2 range $end +$upscope $end +$upscope $end +$var string 1 i2 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 j2 \$tag $end +$scope struct HdlSome $end +$var wire 2 k2 value $end +$var string 1 l2 range $end +$upscope $end +$upscope $end +$var string 1 m2 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 n2 \[0] $end +$var wire 8 o2 \[1] $end +$var wire 8 p2 \[2] $end +$var wire 8 q2 \[3] $end +$var wire 8 r2 \[4] $end +$var wire 8 s2 \[5] $end +$var wire 8 t2 \[6] $end +$var wire 8 u2 \[7] $end +$var wire 8 v2 \[8] $end +$var wire 8 w2 \[9] $end +$var wire 8 x2 \[10] $end +$var wire 8 y2 \[11] $end +$var wire 8 z2 \[12] $end +$var wire 8 {2 \[13] $end +$var wire 8 |2 \[14] $end +$var wire 8 }2 \[15] $end +$upscope $end +$var string 1 ~2 config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 !3 start_pc $end +$var wire 8 "3 fetch_block_id $end +$var string 1 #3 state $end +$var wire 1 $3 canceled $end +$scope struct error $end +$var string 1 %3 \$tag $end +$var string 1 &3 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 '3 \$tag $end +$scope struct HdlSome $end +$var wire 2 (3 value $end +$var string 1 )3 range $end +$upscope $end +$upscope $end +$var string 1 *3 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 +3 \$tag $end +$scope struct HdlSome $end +$var wire 2 ,3 value $end +$var string 1 -3 range $end +$upscope $end +$upscope $end +$var string 1 .3 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 /3 \[0] $end +$var wire 8 03 \[1] $end +$var wire 8 13 \[2] $end +$var wire 8 23 \[3] $end +$var wire 8 33 \[4] $end +$var wire 8 43 \[5] $end +$var wire 8 53 \[6] $end +$var wire 8 63 \[7] $end +$var wire 8 73 \[8] $end +$var wire 8 83 \[9] $end +$var wire 8 93 \[10] $end +$var wire 8 :3 \[11] $end +$var wire 8 ;3 \[12] $end +$var wire 8 <3 \[13] $end +$var wire 8 =3 \[14] $end +$var wire 8 >3 \[15] $end +$upscope $end +$var string 1 ?3 config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 @3 start_pc $end +$var wire 8 A3 fetch_block_id $end +$var string 1 B3 state $end +$var wire 1 C3 canceled $end +$scope struct error $end +$var string 1 D3 \$tag $end +$var string 1 E3 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 F3 \$tag $end +$scope struct HdlSome $end +$var wire 2 G3 value $end +$var string 1 H3 range $end +$upscope $end +$upscope $end +$var string 1 I3 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 J3 \$tag $end +$scope struct HdlSome $end +$var wire 2 K3 value $end +$var string 1 L3 range $end +$upscope $end +$upscope $end +$var string 1 M3 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 N3 \[0] $end +$var wire 8 O3 \[1] $end +$var wire 8 P3 \[2] $end +$var wire 8 Q3 \[3] $end +$var wire 8 R3 \[4] $end +$var wire 8 S3 \[5] $end +$var wire 8 T3 \[6] $end +$var wire 8 U3 \[7] $end +$var wire 8 V3 \[8] $end +$var wire 8 W3 \[9] $end +$var wire 8 X3 \[10] $end +$var wire 8 Y3 \[11] $end +$var wire 8 Z3 \[12] $end +$var wire 8 [3 \[13] $end +$var wire 8 \3 \[14] $end +$var wire 8 ]3 \[15] $end +$upscope $end +$var string 1 ^3 config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 _3 start_pc $end +$var wire 8 `3 fetch_block_id $end +$var string 1 a3 state $end +$var wire 1 b3 canceled $end +$scope struct error $end +$var string 1 c3 \$tag $end +$var string 1 d3 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 e3 \$tag $end +$scope struct HdlSome $end +$var wire 2 f3 value $end +$var string 1 g3 range $end +$upscope $end +$upscope $end +$var string 1 h3 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 i3 \$tag $end +$scope struct HdlSome $end +$var wire 2 j3 value $end +$var string 1 k3 range $end +$upscope $end +$upscope $end +$var string 1 l3 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 m3 \[0] $end +$var wire 8 n3 \[1] $end +$var wire 8 o3 \[2] $end +$var wire 8 p3 \[3] $end +$var wire 8 q3 \[4] $end +$var wire 8 r3 \[5] $end +$var wire 8 s3 \[6] $end +$var wire 8 t3 \[7] $end +$var wire 8 u3 \[8] $end +$var wire 8 v3 \[9] $end +$var wire 8 w3 \[10] $end +$var wire 8 x3 \[11] $end +$var wire 8 y3 \[12] $end +$var wire 8 z3 \[13] $end +$var wire 8 {3 \[14] $end +$var wire 8 |3 \[15] $end +$upscope $end +$var string 1 }3 config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 ~3 start_pc $end +$var wire 8 !4 fetch_block_id $end +$var string 1 "4 state $end +$var wire 1 #4 canceled $end +$scope struct error $end +$var string 1 $4 \$tag $end +$var string 1 %4 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 &4 \$tag $end +$scope struct HdlSome $end +$var wire 2 '4 value $end +$var string 1 (4 range $end +$upscope $end +$upscope $end +$var string 1 )4 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 *4 \$tag $end +$scope struct HdlSome $end +$var wire 2 +4 value $end +$var string 1 ,4 range $end +$upscope $end +$upscope $end +$var string 1 -4 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 .4 \[0] $end +$var wire 8 /4 \[1] $end +$var wire 8 04 \[2] $end +$var wire 8 14 \[3] $end +$var wire 8 24 \[4] $end +$var wire 8 34 \[5] $end +$var wire 8 44 \[6] $end +$var wire 8 54 \[7] $end +$var wire 8 64 \[8] $end +$var wire 8 74 \[9] $end +$var wire 8 84 \[10] $end +$var wire 8 94 \[11] $end +$var wire 8 :4 \[12] $end +$var wire 8 ;4 \[13] $end +$var wire 8 <4 \[14] $end +$var wire 8 =4 \[15] $end +$upscope $end +$var string 1 >4 config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 ?4 start_pc $end +$var wire 8 @4 fetch_block_id $end +$var string 1 A4 state $end +$var wire 1 B4 canceled $end +$scope struct error $end +$var string 1 C4 \$tag $end +$var string 1 D4 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 E4 \$tag $end +$scope struct HdlSome $end +$var wire 2 F4 value $end +$var string 1 G4 range $end +$upscope $end +$upscope $end +$var string 1 H4 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 I4 \$tag $end +$scope struct HdlSome $end +$var wire 2 J4 value $end +$var string 1 K4 range $end +$upscope $end +$upscope $end +$var string 1 L4 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 M4 \[0] $end +$var wire 8 N4 \[1] $end +$var wire 8 O4 \[2] $end +$var wire 8 P4 \[3] $end +$var wire 8 Q4 \[4] $end +$var wire 8 R4 \[5] $end +$var wire 8 S4 \[6] $end +$var wire 8 T4 \[7] $end +$var wire 8 U4 \[8] $end +$var wire 8 V4 \[9] $end +$var wire 8 W4 \[10] $end +$var wire 8 X4 \[11] $end +$var wire 8 Y4 \[12] $end +$var wire 8 Z4 \[13] $end +$var wire 8 [4 \[14] $end +$var wire 8 \4 \[15] $end +$upscope $end +$var string 1 ]4 config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 ^4 start_pc $end +$var wire 8 _4 fetch_block_id $end +$var string 1 `4 state $end +$var wire 1 a4 canceled $end +$scope struct error $end +$var string 1 b4 \$tag $end +$var string 1 c4 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 d4 \$tag $end +$scope struct HdlSome $end +$var wire 2 e4 value $end +$var string 1 f4 range $end +$upscope $end +$upscope $end +$var string 1 g4 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 h4 \$tag $end +$scope struct HdlSome $end +$var wire 2 i4 value $end +$var string 1 j4 range $end +$upscope $end +$upscope $end +$var string 1 k4 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 l4 \[0] $end +$var wire 8 m4 \[1] $end +$var wire 8 n4 \[2] $end +$var wire 8 o4 \[3] $end +$var wire 8 p4 \[4] $end +$var wire 8 q4 \[5] $end +$var wire 8 r4 \[6] $end +$var wire 8 s4 \[7] $end +$var wire 8 t4 \[8] $end +$var wire 8 u4 \[9] $end +$var wire 8 v4 \[10] $end +$var wire 8 w4 \[11] $end +$var wire 8 x4 \[12] $end +$var wire 8 y4 \[13] $end +$var wire 8 z4 \[14] $end +$var wire 8 {4 \[15] $end +$upscope $end +$var string 1 |4 config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 }4 start_pc $end +$var wire 8 ~4 fetch_block_id $end +$var string 1 !5 state $end +$var wire 1 "5 canceled $end +$scope struct error $end +$var string 1 #5 \$tag $end +$var string 1 $5 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 %5 \$tag $end +$scope struct HdlSome $end +$var wire 2 &5 value $end +$var string 1 '5 range $end +$upscope $end +$upscope $end +$var string 1 (5 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 )5 \$tag $end +$scope struct HdlSome $end +$var wire 2 *5 value $end +$var string 1 +5 range $end +$upscope $end +$upscope $end +$var string 1 ,5 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 -5 \[0] $end +$var wire 8 .5 \[1] $end +$var wire 8 /5 \[2] $end +$var wire 8 05 \[3] $end +$var wire 8 15 \[4] $end +$var wire 8 25 \[5] $end +$var wire 8 35 \[6] $end +$var wire 8 45 \[7] $end +$var wire 8 55 \[8] $end +$var wire 8 65 \[9] $end +$var wire 8 75 \[10] $end +$var wire 8 85 \[11] $end +$var wire 8 95 \[12] $end +$var wire 8 :5 \[13] $end +$var wire 8 ;5 \[14] $end +$var wire 8 <5 \[15] $end +$upscope $end +$var string 1 =5 config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 >5 start_pc $end +$var wire 8 ?5 fetch_block_id $end +$var string 1 @5 state $end +$var wire 1 A5 canceled $end +$scope struct error $end +$var string 1 B5 \$tag $end +$var string 1 C5 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 D5 \$tag $end +$scope struct HdlSome $end +$var wire 2 E5 value $end +$var string 1 F5 range $end +$upscope $end +$upscope $end +$var string 1 G5 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 H5 \$tag $end +$scope struct HdlSome $end +$var wire 2 I5 value $end +$var string 1 J5 range $end +$upscope $end +$upscope $end +$var string 1 K5 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 L5 \[0] $end +$var wire 8 M5 \[1] $end +$var wire 8 N5 \[2] $end +$var wire 8 O5 \[3] $end +$var wire 8 P5 \[4] $end +$var wire 8 Q5 \[5] $end +$var wire 8 R5 \[6] $end +$var wire 8 S5 \[7] $end +$var wire 8 T5 \[8] $end +$var wire 8 U5 \[9] $end +$var wire 8 V5 \[10] $end +$var wire 8 W5 \[11] $end +$var wire 8 X5 \[12] $end +$var wire 8 Y5 \[13] $end +$var wire 8 Z5 \[14] $end +$var wire 8 [5 \[15] $end +$upscope $end +$var string 1 \5 config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 ]5 start_pc $end +$var wire 8 ^5 fetch_block_id $end +$var string 1 _5 state $end +$var wire 1 `5 canceled $end +$scope struct error $end +$var string 1 a5 \$tag $end +$var string 1 b5 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 c5 \$tag $end +$scope struct HdlSome $end +$var wire 2 d5 value $end +$var string 1 e5 range $end +$upscope $end +$upscope $end +$var string 1 f5 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 g5 \$tag $end +$scope struct HdlSome $end +$var wire 2 h5 value $end +$var string 1 i5 range $end +$upscope $end +$upscope $end +$var string 1 j5 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 k5 \[0] $end +$var wire 8 l5 \[1] $end +$var wire 8 m5 \[2] $end +$var wire 8 n5 \[3] $end +$var wire 8 o5 \[4] $end +$var wire 8 p5 \[5] $end +$var wire 8 q5 \[6] $end +$var wire 8 r5 \[7] $end +$var wire 8 s5 \[8] $end +$var wire 8 t5 \[9] $end +$var wire 8 u5 \[10] $end +$var wire 8 v5 \[11] $end +$var wire 8 w5 \[12] $end +$var wire 8 x5 \[13] $end +$var wire 8 y5 \[14] $end +$var wire 8 z5 \[15] $end +$upscope $end +$var string 1 {5 config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 |5 start_pc $end +$var wire 8 }5 fetch_block_id $end +$var string 1 ~5 state $end +$var wire 1 !6 canceled $end +$scope struct error $end +$var string 1 "6 \$tag $end +$var string 1 #6 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 $6 \$tag $end +$scope struct HdlSome $end +$var wire 2 %6 value $end +$var string 1 &6 range $end +$upscope $end +$upscope $end +$var string 1 '6 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 (6 \$tag $end +$scope struct HdlSome $end +$var wire 2 )6 value $end +$var string 1 *6 range $end +$upscope $end +$upscope $end +$var string 1 +6 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ,6 \[0] $end +$var wire 8 -6 \[1] $end +$var wire 8 .6 \[2] $end +$var wire 8 /6 \[3] $end +$var wire 8 06 \[4] $end +$var wire 8 16 \[5] $end +$var wire 8 26 \[6] $end +$var wire 8 36 \[7] $end +$var wire 8 46 \[8] $end +$var wire 8 56 \[9] $end +$var wire 8 66 \[10] $end +$var wire 8 76 \[11] $end +$var wire 8 86 \[12] $end +$var wire 8 96 \[13] $end +$var wire 8 :6 \[14] $end +$var wire 8 ;6 \[15] $end +$upscope $end +$var string 1 <6 config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 =6 start_pc $end +$var wire 8 >6 fetch_block_id $end +$var string 1 ?6 state $end +$var wire 1 @6 canceled $end +$scope struct error $end +$var string 1 A6 \$tag $end +$var string 1 B6 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 C6 \$tag $end +$scope struct HdlSome $end +$var wire 2 D6 value $end +$var string 1 E6 range $end +$upscope $end +$upscope $end +$var string 1 F6 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 G6 \$tag $end +$scope struct HdlSome $end +$var wire 2 H6 value $end +$var string 1 I6 range $end +$upscope $end +$upscope $end +$var string 1 J6 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 K6 \[0] $end +$var wire 8 L6 \[1] $end +$var wire 8 M6 \[2] $end +$var wire 8 N6 \[3] $end +$var wire 8 O6 \[4] $end +$var wire 8 P6 \[5] $end +$var wire 8 Q6 \[6] $end +$var wire 8 R6 \[7] $end +$var wire 8 S6 \[8] $end +$var wire 8 T6 \[9] $end +$var wire 8 U6 \[10] $end +$var wire 8 V6 \[11] $end +$var wire 8 W6 \[12] $end +$var wire 8 X6 \[13] $end +$var wire 8 Y6 \[14] $end +$var wire 8 Z6 \[15] $end +$upscope $end +$var string 1 [6 config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 \6 start_pc $end +$var wire 8 ]6 fetch_block_id $end +$var string 1 ^6 state $end +$var wire 1 _6 canceled $end +$scope struct error $end +$var string 1 `6 \$tag $end +$var string 1 a6 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 b6 \$tag $end +$scope struct HdlSome $end +$var wire 2 c6 value $end +$var string 1 d6 range $end +$upscope $end +$upscope $end +$var string 1 e6 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 f6 \$tag $end +$scope struct HdlSome $end +$var wire 2 g6 value $end +$var string 1 h6 range $end +$upscope $end +$upscope $end +$var string 1 i6 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 j6 \[0] $end +$var wire 8 k6 \[1] $end +$var wire 8 l6 \[2] $end +$var wire 8 m6 \[3] $end +$var wire 8 n6 \[4] $end +$var wire 8 o6 \[5] $end +$var wire 8 p6 \[6] $end +$var wire 8 q6 \[7] $end +$var wire 8 r6 \[8] $end +$var wire 8 s6 \[9] $end +$var wire 8 t6 \[10] $end +$var wire 8 u6 \[11] $end +$var wire 8 v6 \[12] $end +$var wire 8 w6 \[13] $end +$var wire 8 x6 \[14] $end +$var wire 8 y6 \[15] $end +$upscope $end +$var string 1 z6 config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 {6 start_pc $end +$var wire 8 |6 fetch_block_id $end +$var string 1 }6 state $end +$var wire 1 ~6 canceled $end +$scope struct error $end +$var string 1 !7 \$tag $end +$var string 1 "7 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 #7 \$tag $end +$scope struct HdlSome $end +$var wire 2 $7 value $end +$var string 1 %7 range $end +$upscope $end +$upscope $end +$var string 1 &7 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 '7 \$tag $end +$scope struct HdlSome $end +$var wire 2 (7 value $end +$var string 1 )7 range $end +$upscope $end +$upscope $end +$var string 1 *7 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 +7 \[0] $end +$var wire 8 ,7 \[1] $end +$var wire 8 -7 \[2] $end +$var wire 8 .7 \[3] $end +$var wire 8 /7 \[4] $end +$var wire 8 07 \[5] $end +$var wire 8 17 \[6] $end +$var wire 8 27 \[7] $end +$var wire 8 37 \[8] $end +$var wire 8 47 \[9] $end +$var wire 8 57 \[10] $end +$var wire 8 67 \[11] $end +$var wire 8 77 \[12] $end +$var wire 8 87 \[13] $end +$var wire 8 97 \[14] $end +$var wire 8 :7 \[15] $end +$upscope $end +$var string 1 ;7 config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 <7 start_pc $end +$var wire 8 =7 fetch_block_id $end +$var string 1 >7 state $end +$var wire 1 ?7 canceled $end +$scope struct error $end +$var string 1 @7 \$tag $end +$var string 1 A7 HdlSome $end +$upscope $end +$scope struct fill_indexes_to_start $end +$scope struct next_index $end +$var string 1 B7 \$tag $end +$scope struct HdlSome $end +$var wire 2 C7 value $end +$var string 1 D7 range $end +$upscope $end +$upscope $end +$var string 1 E7 config $end +$upscope $end +$scope struct fill_indexes_to_finish $end +$scope struct next_index $end +$var string 1 F7 \$tag $end +$scope struct HdlSome $end +$var wire 2 G7 value $end +$var string 1 H7 range $end +$upscope $end +$upscope $end +$var string 1 I7 config $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 J7 \[0] $end +$var wire 8 K7 \[1] $end +$var wire 8 L7 \[2] $end +$var wire 8 M7 \[3] $end +$var wire 8 N7 \[4] $end +$var wire 8 O7 \[5] $end +$var wire 8 P7 \[6] $end +$var wire 8 Q7 \[7] $end +$var wire 8 R7 \[8] $end +$var wire 8 S7 \[9] $end +$var wire 8 T7 \[10] $end +$var wire 8 U7 \[11] $end +$var wire 8 V7 \[12] $end +$var wire 8 W7 \[13] $end +$var wire 8 X7 \[14] $end +$var wire 8 Y7 \[15] $end +$upscope $end +$var string 1 Z7 config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 [7 value $end +$var string 1 \7 range $end +$upscope $end +$upscope $end +$var string 1 ]7 config $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mock_memory $end +$scope struct cd $end +$var wire 1 OC clk $end +$var wire 1 PC rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 QC \$tag $end +$scope struct HdlSome $end +$var string 1 RC kind $end +$var wire 64 SC addr $end +$scope struct write_data $end +$var wire 8 TC \[0] $end +$var wire 8 UC \[1] $end +$var wire 8 VC \[2] $end +$var wire 8 WC \[3] $end +$var wire 8 XC \[4] $end +$var wire 8 YC \[5] $end +$var wire 8 ZC \[6] $end +$var wire 8 [C \[7] $end +$var wire 8 \C \[8] $end +$var wire 8 ]C \[9] $end +$var wire 8 ^C \[10] $end +$var wire 8 _C \[11] $end +$var wire 8 `C \[12] $end +$var wire 8 aC \[13] $end +$var wire 8 bC \[14] $end +$var wire 8 cC \[15] $end +$upscope $end +$var string 1 dC config $end +$upscope $end +$upscope $end +$var wire 1 eC ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 fC \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 gC \$tag $end +$var string 1 hC Success $end +$var string 1 iC Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 jC \[0] $end +$var wire 8 kC \[1] $end +$var wire 8 lC \[2] $end +$var wire 8 mC \[3] $end +$var wire 8 nC \[4] $end +$var wire 8 oC \[5] $end +$var wire 8 pC \[6] $end +$var wire 8 qC \[7] $end +$var wire 8 rC \[8] $end +$var wire 8 sC \[9] $end +$var wire 8 tC \[10] $end +$var wire 8 uC \[11] $end +$var wire 8 vC \[12] $end +$var wire 8 wC \[13] $end +$var wire 8 xC \[14] $end +$var wire 8 yC \[15] $end +$upscope $end +$var string 1 zC config $end +$upscope $end +$upscope $end +$var wire 1 {C ready $end +$upscope $end +$var string 1 |C config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 }C addr $end +$var wire 8 ~C cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 !D addr $end +$var wire 8 "D cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 #D addr $end +$var wire 8 $D cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 %D addr $end +$var wire 8 &D cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 'D addr $end +$var wire 8 (D cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 )D addr $end +$var wire 8 *D cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 +D addr $end +$var wire 8 ,D cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 -D addr $end +$var wire 8 .D cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 /D addr $end +$var wire 8 0D cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 1D addr $end +$var wire 8 2D cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 3D addr $end +$var wire 8 4D cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 5D addr $end +$var wire 8 6D cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 7D addr $end +$var wire 8 8D cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 9D addr $end +$var wire 8 :D cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 ;D addr $end +$var wire 8 D cycles_left $end +$upscope $end +$scope struct \[16] $end +$var wire 64 ?D addr $end +$var wire 8 @D cycles_left $end +$upscope $end +$scope struct \[17] $end +$var wire 64 AD addr $end +$var wire 8 BD cycles_left $end +$upscope $end +$scope struct \[18] $end +$var wire 64 CD addr $end +$var wire 8 DD cycles_left $end +$upscope $end +$scope struct \[19] $end +$var wire 64 ED addr $end +$var wire 8 FD cycles_left $end +$upscope $end +$scope struct \[20] $end +$var wire 64 GD addr $end +$var wire 8 HD cycles_left $end +$upscope $end +$scope struct \[21] $end +$var wire 64 ID addr $end +$var wire 8 JD cycles_left $end +$upscope $end +$scope struct \[22] $end +$var wire 64 KD addr $end +$var wire 8 LD cycles_left $end +$upscope $end +$scope struct \[23] $end +$var wire 64 MD addr $end +$var wire 8 ND cycles_left $end +$upscope $end +$scope struct \[24] $end +$var wire 64 OD addr $end +$var wire 8 PD cycles_left $end +$upscope $end +$scope struct \[25] $end +$var wire 64 QD addr $end +$var wire 8 RD cycles_left $end +$upscope $end +$scope struct \[26] $end +$var wire 64 SD addr $end +$var wire 8 TD cycles_left $end +$upscope $end +$scope struct \[27] $end +$var wire 64 UD addr $end +$var wire 8 VD cycles_left $end +$upscope $end +$scope struct \[28] $end +$var wire 64 WD addr $end +$var wire 8 XD cycles_left $end +$upscope $end +$scope struct \[29] $end +$var wire 64 YD addr $end +$var wire 8 ZD cycles_left $end +$upscope $end +$scope struct \[30] $end +$var wire 64 [D addr $end +$var wire 8 \D cycles_left $end +$upscope $end +$scope struct \[31] $end +$var wire 64 ]D addr $end +$var wire 8 ^D cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 6 _D value $end +$var string 1 `D range $end +$upscope $end +$upscope $end +$upscope $end +$scope module mock_memory_2 $end +$scope struct cd $end +$var wire 1 =B clk $end +$var wire 1 >B rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 ?B \$tag $end +$scope struct HdlSome $end +$var string 1 @B kind $end +$var wire 64 AB addr $end +$scope struct write_data $end +$var wire 8 BB \[0] $end +$var wire 8 CB \[1] $end +$var wire 8 DB \[2] $end +$var wire 8 EB \[3] $end +$var wire 8 FB \[4] $end +$var wire 8 GB \[5] $end +$var wire 8 HB \[6] $end +$var wire 8 IB \[7] $end +$var wire 8 JB \[8] $end +$var wire 8 KB \[9] $end +$var wire 8 LB \[10] $end +$var wire 8 MB \[11] $end +$var wire 8 NB \[12] $end +$var wire 8 OB \[13] $end +$var wire 8 PB \[14] $end +$var wire 8 QB \[15] $end +$upscope $end +$var string 1 RB config $end +$upscope $end +$upscope $end +$var wire 1 SB ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 TB \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 UB \$tag $end +$var string 1 VB Success $end +$var string 1 WB Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 XB \[0] $end +$var wire 8 YB \[1] $end +$var wire 8 ZB \[2] $end +$var wire 8 [B \[3] $end +$var wire 8 \B \[4] $end +$var wire 8 ]B \[5] $end +$var wire 8 ^B \[6] $end +$var wire 8 _B \[7] $end +$var wire 8 `B \[8] $end +$var wire 8 aB \[9] $end +$var wire 8 bB \[10] $end +$var wire 8 cB \[11] $end +$var wire 8 dB \[12] $end +$var wire 8 eB \[13] $end +$var wire 8 fB \[14] $end +$var wire 8 gB \[15] $end +$upscope $end +$var string 1 hB config $end +$upscope $end +$upscope $end +$var wire 1 iB ready $end +$upscope $end +$var string 1 jB config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 kB addr $end +$var wire 8 lB cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 mB addr $end +$var wire 8 nB cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 oB addr $end +$var wire 8 pB cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 qB addr $end +$var wire 8 rB cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 sB addr $end +$var wire 8 tB cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 uB addr $end +$var wire 8 vB cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 wB addr $end +$var wire 8 xB cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 yB addr $end +$var wire 8 zB cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 {B addr $end +$var wire 8 |B cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 }B addr $end +$var wire 8 ~B cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 !C addr $end +$var wire 8 "C cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 #C addr $end +$var wire 8 $C cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 %C addr $end +$var wire 8 &C cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 'C addr $end +$var wire 8 (C cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 )C addr $end +$var wire 8 *C cycles_left $end +$upscope $end +$scope struct \[15] $end +$var wire 64 +C addr $end +$var wire 8 ,C cycles_left $end +$upscope $end +$scope struct \[16] $end +$var wire 64 -C addr $end +$var wire 8 .C cycles_left $end +$upscope $end +$scope struct \[17] $end +$var wire 64 /C addr $end +$var wire 8 0C cycles_left $end +$upscope $end +$scope struct \[18] $end +$var wire 64 1C addr $end +$var wire 8 2C cycles_left $end +$upscope $end +$scope struct \[19] $end +$var wire 64 3C addr $end +$var wire 8 4C cycles_left $end +$upscope $end +$scope struct \[20] $end +$var wire 64 5C addr $end +$var wire 8 6C cycles_left $end +$upscope $end +$scope struct \[21] $end +$var wire 64 7C addr $end +$var wire 8 8C cycles_left $end +$upscope $end +$scope struct \[22] $end +$var wire 64 9C addr $end +$var wire 8 :C cycles_left $end +$upscope $end +$scope struct \[23] $end +$var wire 64 ;C addr $end +$var wire 8 C cycles_left $end +$upscope $end +$scope struct \[25] $end +$var wire 64 ?C addr $end +$var wire 8 @C cycles_left $end +$upscope $end +$scope struct \[26] $end +$var wire 64 AC addr $end +$var wire 8 BC cycles_left $end +$upscope $end +$scope struct \[27] $end +$var wire 64 CC addr $end +$var wire 8 DC cycles_left $end +$upscope $end +$scope struct \[28] $end +$var wire 64 EC addr $end +$var wire 8 FC cycles_left $end +$upscope $end +$scope struct \[29] $end +$var wire 64 GC addr $end +$var wire 8 HC cycles_left $end +$upscope $end +$scope struct \[30] $end +$var wire 64 IC addr $end +$var wire 8 JC cycles_left $end +$upscope $end +$scope struct \[31] $end +$var wire 64 KC addr $end +$var wire 8 LC cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 6 MC value $end +$var string 1 NC range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +sHdlSome\x20(1) # +b1000000000000 $ +b0 % +0& +sHdlNone\x20(0) ' +b0 ( +sPhantomConst(\"1..=16\") ) +0* +sHdlNone\x20(0) + +b0 , +b0 - +b0 . +b0 / +b0 0 +b0 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +b0 7 +b0 8 +b0 9 +b0 : +b0 ; +b0 < +sPhantomConst(\"0..=16\") = +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) > +sHdlNone\x20(0) ? +b0 @ +b0 A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +b0 J +b0 K +b0 L +b0 M +b0 N +b0 O +b0 P +b0 Q +sHdlNone\x20(0) R +sGeneric\x20(0) S +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) T +1U +sHdlNone\x20(0) V +b0 W +sPhantomConst(\"1..=16\") X +0Y +1Z +sHdlNone\x20(0) [ +sRead\x20(0) \ +b0 ] +b0 ^ +b0 _ +b0 ` +b0 a +b0 b +b0 c +b0 d +b0 e +b0 f +b0 g +b0 h +b0 i +b0 j +b0 k +b0 l +b0 m +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) n +0o +sHdlNone\x20(0) p +sSuccess\x20(0) q +sRead\x20(0) r +sGeneric\x20(0) s +b0 t +b0 u +b0 v +b0 w +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b0 "" +b0 #" +b0 $" +b0 %" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) &" +0'" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (" +sHdlSome\x20(1) )" +b1000000000000 *" +b0 +" +0," +sHdlNone\x20(0) -" +b0 ." +sPhantomConst(\"1..=16\") /" +00" +sHdlNone\x20(0) 1" +b0 2" +b0 3" +b0 4" +b0 5" +b0 6" +b0 7" +b0 8" +b0 9" +b0 :" +b0 ;" +b0 <" +b0 =" +b0 >" +b0 ?" +b0 @" +b0 A" +b0 B" +sPhantomConst(\"0..=16\") C" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) D" +sHdlNone\x20(0) E" +b0 F" +b0 G" +b0 H" +b0 I" +b0 J" +b0 K" +b0 L" +b0 M" +b0 N" +b0 O" +b0 P" +b0 Q" +b0 R" +b0 S" +b0 T" +b0 U" +b0 V" +b0 W" +sHdlNone\x20(0) X" +sGeneric\x20(0) Y" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z" +1[" +sHdlNone\x20(0) \" +b0 ]" +sPhantomConst(\"1..=16\") ^" +0_" +1`" +sHdlNone\x20(0) a" +sRead\x20(0) b" +b0 c" +b0 d" +b0 e" +b0 f" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +b0 o" +b0 p" +b0 q" +b0 r" +b0 s" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) t" +0u" +sHdlNone\x20(0) v" +sSuccess\x20(0) w" +sRead\x20(0) x" +sGeneric\x20(0) y" +b0 z" +b0 {" +b0 |" +b0 }" +b0 ~" +b0 !# +b0 "# +b0 ## +b0 $# +b0 %# +b0 &# +b0 '# +b0 (# +b0 )# +b0 *# +b0 +# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,# +0-# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .# +sHdlSome\x20(1) /# +b1000000000000 0# +b0 1# +02# +sHdlNone\x20(0) 3# +b0 4# +sPhantomConst(\"1..=16\") 5# +06# +sHdlNone\x20(0) 7# +b0 8# +b0 9# +b0 :# +b0 ;# +b0 <# +b0 =# +b0 ># +b0 ?# +b0 @# +b0 A# +b0 B# +b0 C# +b0 D# +b0 E# +b0 F# +b0 G# +b0 H# +sPhantomConst(\"0..=16\") I# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J# +sHdlNone\x20(0) K# +b0 L# +b0 M# +b0 N# +b0 O# +b0 P# +b0 Q# +b0 R# +b0 S# +b0 T# +b0 U# +b0 V# +b0 W# +b0 X# +b0 Y# +b0 Z# +b0 [# +b0 \# +b0 ]# +sHdlNone\x20(0) ^# +sGeneric\x20(0) _# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `# +1a# +sHdlNone\x20(0) b# +b0 c# +sPhantomConst(\"1..=16\") d# +b0 e# +b0 f# +b0 g# +b0 h# +b0 i# +b0 j# +b0 k# +b0 l# +b0 m# +b0 n# +b0 o# +b0 p# +b0 q# +b0 r# +b0 s# +b0 t# +b0 u# +b0 v# +b0 w# +b0 x# +b0 y# +b0 z# +b0 {# +b0 |# +b0 }# +b0 ~# +b0 !$ +b0 "$ +b0 #$ +b0 $$ +b0 %$ +b0 &$ +b0 '$ +b0 ($ +b0 )$ +b0 *$ +b0 +$ +b0 ,$ +b0 -$ +b0 .$ +b0 /$ +b0 0$ +b0 1$ +b0 2$ +b0 3$ +b0 4$ +b0 5$ +b0 6$ +b0 7$ +b0 8$ +b0 9$ +b0 :$ +b0 ;$ +b0 <$ +b0 =$ +b0 >$ +b0 ?$ +b0 @$ +b0 A$ +b0 B$ +b0 C$ +b0 D$ +b0 E$ +b0 F$ +sHdlNone\x20(0) G$ +b0 H$ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) I$ +b0 J$ +b0 K$ +b0 L$ +b0 M$ +b0 N$ +b0 O$ +b0 P$ +b0 Q$ +b0 R$ +b0 S$ +b0 T$ +b0 U$ +b0 V$ +b0 W$ +b0 X$ +b0 Y$ +b0 Z$ +b0 [$ +b0 \$ +b0 ]$ +b0 ^$ +b0 _$ +b0 `$ +b0 a$ +b0 b$ +b0 c$ +b0 d$ +b0 e$ +b0 f$ +b0 g$ +b0 h$ +b0 i$ +b0 j$ +b0 k$ +b0 l$ +b0 m$ +b0 n$ +b0 o$ +b0 p$ +b0 q$ +b0 r$ +b0 s$ +b0 t$ +b0 u$ +b0 v$ +b0 w$ +b0 x$ +b0 y$ +b0 z$ +b0 {$ +b0 |$ +b0 }$ +b0 ~$ +b0 !% +b0 "% +b0 #% +b0 $% +b0 %% +b0 &% +b0 '% +b0 (% +b0 )% +b0 *% +b0 +% +sHdlNone\x20(0) ,% +b0 -% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .% +b0 /% +b0 0% +b0 1% +b0 2% +b0 3% +b0 4% +b0 5% +b0 6% +b0 7% +b0 8% +b0 9% +b0 :% +b0 ;% +b0 <% +b0 =% +b0 >% +b0 ?% +b0 @% +b0 A% +b0 B% +b0 C% +b0 D% +b0 E% +b0 F% +b0 G% +b0 H% +b0 I% +b0 J% +b0 K% +b0 L% +b0 M% +b0 N% +b0 O% +b0 P% +b0 Q% +b0 R% +b0 S% +b0 T% +b0 U% +b0 V% +b0 W% +b0 X% +b0 Y% +b0 Z% +b0 [% +b0 \% +b0 ]% +b0 ^% +b0 _% +b0 `% +b0 a% +b0 b% +b0 c% +b0 d% +b0 e% +b0 f% +b0 g% +b0 h% +b0 i% +b0 j% +b0 k% +b0 l% +b0 m% +b0 n% +sHdlNone\x20(0) o% +b0 p% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) q% +b0 r% +b0 s% +b0 t% +b0 u% +b0 v% +b0 w% +b0 x% +b0 y% +b0 z% +b0 {% +b0 |% +b0 }% +b0 ~% +b0 !& +b0 "& +b0 #& +b0 $& +b0 %& +b0 && +b0 '& +b0 (& +b0 )& +b0 *& +b0 +& +b0 ,& +b0 -& +b0 .& +b0 /& +b0 0& +b0 1& +b0 2& +b0 3& +b0 4& +b0 5& +b0 6& +b0 7& +b0 8& +b0 9& +b0 :& +b0 ;& +b0 <& +b0 =& +b0 >& +b0 ?& +b0 @& +b0 A& +b0 B& +b0 C& +b0 D& +b0 E& +b0 F& +b0 G& +b0 H& +b0 I& +b0 J& +b0 K& +b0 L& +b0 M& +b0 N& +b0 O& +b0 P& +b0 Q& +b0 R& +b0 S& +sHdlNone\x20(0) T& +b0 U& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) V& +b0 W& +b0 X& +b0 Y& +b0 Z& +b0 [& +b0 \& +b0 ]& +b0 ^& +b0 _& +b0 `& +b0 a& +b0 b& +b0 c& +b0 d& +b0 e& +b0 f& +b0 g& +b0 h& +b0 i& +b0 j& +b0 k& +b0 l& +b0 m& +b0 n& +b0 o& +b0 p& +b0 q& +b0 r& +b0 s& +b0 t& +b0 u& +b0 v& +b0 w& +b0 x& +b0 y& +b0 z& +b0 {& +b0 |& +b0 }& +b0 ~& +b0 !' +b0 "' +b0 #' +b0 $' +b0 %' +b0 &' +b0 '' +b0 (' +b0 )' +b0 *' +b0 +' +b0 ,' +b0 -' +b0 .' +b0 /' +b0 0' +b0 1' +b0 2' +b0 3' +b0 4' +b0 5' +b0 6' +b0 7' +b0 8' +sHdlNone\x20(0) 9' +b0 :' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ;' +b0 <' +b0 =' +b0 >' +b0 ?' +b0 @' +b0 A' +b0 B' +b0 C' +b0 D' +b0 E' +b0 F' +b0 G' +b0 H' +b0 I' +b0 J' +b0 K' +b0 L' +b0 M' +b0 N' +b0 O' +b0 P' +b0 Q' +b0 R' +b0 S' +b0 T' +b0 U' +b0 V' +b0 W' +b0 X' +b0 Y' +b0 Z' +b0 [' +b0 \' +b0 ]' +b0 ^' +b0 _' +b0 `' +b0 a' +b0 b' +b0 c' +b0 d' +b0 e' +b0 f' +b0 g' +b0 h' +b0 i' +b0 j' +b0 k' +b0 l' +b0 m' +b0 n' +b0 o' +b0 p' +b0 q' +b0 r' +b0 s' +b0 t' +b0 u' +b0 v' +b0 w' +b0 x' +b0 y' +b0 z' +b0 {' +sHdlNone\x20(0) |' +b0 }' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~' +b0 !( +b0 "( +b0 #( +b0 $( +b0 %( +b0 &( +b0 '( +b0 (( +b0 )( +b0 *( +b0 +( +b0 ,( +b0 -( +b0 .( +b0 /( +b0 0( +b0 1( +b0 2( +b0 3( +b0 4( +b0 5( +b0 6( +b0 7( +b0 8( +b0 9( +b0 :( +b0 ;( +b0 <( +b0 =( +b0 >( +b0 ?( +b0 @( +b0 A( +b0 B( +b0 C( +b0 D( +b0 E( +b0 F( +b0 G( +b0 H( +b0 I( +b0 J( +b0 K( +b0 L( +b0 M( +b0 N( +b0 O( +b0 P( +b0 Q( +b0 R( +b0 S( +b0 T( +b0 U( +b0 V( +b0 W( +b0 X( +b0 Y( +b0 Z( +b0 [( +b0 \( +b0 ]( +b0 ^( +b0 _( +b0 `( +sHdlNone\x20(0) a( +b0 b( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) c( +b0 d( +b0 e( +b0 f( +b0 g( +b0 h( +b0 i( +b0 j( +b0 k( +b0 l( +b0 m( +b0 n( +b0 o( +b0 p( +b0 q( +b0 r( +b0 s( +b0 t( +b0 u( +b0 v( +b0 w( +b0 x( +b0 y( +b0 z( +b0 {( +b0 |( +b0 }( +b0 ~( +b0 !) +b0 ") +b0 #) +b0 $) +b0 %) +b0 &) +b0 ') +b0 () +b0 )) +b0 *) +b0 +) +b0 ,) +b0 -) +b0 .) +b0 /) +b0 0) +b0 1) +b0 2) +b0 3) +b0 4) +b0 5) +b0 6) +b0 7) +b0 8) +b0 9) +b0 :) +b0 ;) +b0 <) +b0 =) +b0 >) +b0 ?) +b0 @) +b0 A) +b0 B) +b0 C) +b0 D) +b0 E) +sHdlNone\x20(0) F) +b0 G) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) H) +b0 I) +b0 J) +b0 K) +b0 L) +b0 M) +b0 N) +b0 O) +b0 P) +b0 Q) +b0 R) +b0 S) +b0 T) +b0 U) +b0 V) +b0 W) +b0 X) +b0 Y) +b0 Z) +b0 [) +b0 \) +b0 ]) +b0 ^) +b0 _) +b0 `) +b0 a) +b0 b) +b0 c) +b0 d) +b0 e) +b0 f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +b0 m) +b0 n) +b0 o) +b0 p) +b0 q) +b0 r) +b0 s) +b0 t) +b0 u) +b0 v) +b0 w) +b0 x) +b0 y) +b0 z) +b0 {) +b0 |) +b0 }) +b0 ~) +b0 !* +b0 "* +b0 #* +b0 $* +b0 %* +b0 &* +b0 '* +b0 (* +b0 )* +b0 ** +sHdlNone\x20(0) +* +b0 ,* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -* +b0 .* +b0 /* +b0 0* +b0 1* +b0 2* +b0 3* +b0 4* +b0 5* +b0 6* +b0 7* +b0 8* +b0 9* +b0 :* +b0 ;* +b0 <* +b0 =* +b0 >* +b0 ?* +b0 @* +b0 A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b0 H* +b0 I* +b0 J* +b0 K* +b0 L* +b0 M* +b0 N* +b0 O* +b0 P* +b0 Q* +b0 R* +b0 S* +b0 T* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +b0 \* +b0 ]* +b0 ^* +b0 _* +b0 `* +b0 a* +b0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +sHdlNone\x20(0) n* +b0 o* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p* +b0 q* +b0 r* +b0 s* +b0 t* +b0 u* +b0 v* +b0 w* +b0 x* +b0 y* +b0 z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +b0 #+ +b0 $+ +b0 %+ +b0 &+ +b0 '+ +b0 (+ +b0 )+ +b0 *+ +b0 ++ +b0 ,+ +b0 -+ +b0 .+ +b0 /+ +b0 0+ +b0 1+ +b0 2+ +b0 3+ +b0 4+ +b0 5+ +b0 6+ +b0 7+ +b0 8+ +b0 9+ +b0 :+ +b0 ;+ +b0 <+ +b0 =+ +b0 >+ +b0 ?+ +b0 @+ +b0 A+ +b0 B+ +b0 C+ +b0 D+ +b0 E+ +b0 F+ +b0 G+ +b0 H+ +b0 I+ +b0 J+ +b0 K+ +b0 L+ +b0 M+ +b0 N+ +b0 O+ +b0 P+ +b0 Q+ +b0 R+ +sHdlNone\x20(0) S+ +b0 T+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) U+ +b0 V+ +b0 W+ +b0 X+ +b0 Y+ +b0 Z+ +b0 [+ +b0 \+ +b0 ]+ +b0 ^+ +b0 _+ +b0 `+ +b0 a+ +b0 b+ +b0 c+ +b0 d+ +b0 e+ +b0 f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b0 l+ +b0 m+ +b0 n+ +b0 o+ +b0 p+ +b0 q+ +b0 r+ +b0 s+ +b0 t+ +b0 u+ +b0 v+ +b0 w+ +b0 x+ +b0 y+ +b0 z+ +b0 {+ +b0 |+ +b0 }+ +b0 ~+ +b0 !, +b0 ", +b0 #, +b0 $, +b0 %, +b0 &, +b0 ', +b0 (, +b0 ), +b0 *, +b0 +, +b0 ,, +b0 -, +b0 ., +b0 /, +b0 0, +b0 1, +b0 2, +b0 3, +b0 4, +b0 5, +b0 6, +b0 7, +sHdlNone\x20(0) 8, +b0 9, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :, +b0 ;, +b0 <, +b0 =, +b0 >, +b0 ?, +b0 @, +b0 A, +b0 B, +b0 C, +b0 D, +b0 E, +b0 F, +b0 G, +b0 H, +b0 I, +b0 J, +b0 K, +b0 L, +b0 M, +b0 N, +b0 O, +b0 P, +b0 Q, +b0 R, +b0 S, +b0 T, +b0 U, +b0 V, +b0 W, +b0 X, +b0 Y, +b0 Z, +b0 [, +b0 \, +b0 ], +b0 ^, +b0 _, +b0 `, +b0 a, +b0 b, +b0 c, +b0 d, +b0 e, +b0 f, +b0 g, +b0 h, +b0 i, +b0 j, +b0 k, +b0 l, +b0 m, +b0 n, +b0 o, +b0 p, +b0 q, +b0 r, +b0 s, +b0 t, +b0 u, +b0 v, +b0 w, +b0 x, +b0 y, +b0 z, +sHdlNone\x20(0) {, +b0 |, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }, +b0 ~, +b0 !- +b0 "- +b0 #- +b0 $- +b0 %- +b0 &- +b0 '- +b0 (- +b0 )- +b0 *- +b0 +- +b0 ,- +b0 -- +b0 .- +b0 /- +b0 0- +b0 1- +b0 2- +b0 3- +b0 4- +b0 5- +b0 6- +b0 7- +b0 8- +b0 9- +b0 :- +b0 ;- +b0 <- +b0 =- +b0 >- +b0 ?- +b0 @- +b0 A- +b0 B- +b0 C- +b0 D- +b0 E- +b0 F- +b0 G- +b0 H- +b0 I- +b0 J- +b0 K- +b0 L- +b0 M- +b0 N- +b0 O- +b0 P- +b0 Q- +b0 R- +b0 S- +b0 T- +b0 U- +b0 V- +b0 W- +b0 X- +b0 Y- +b0 Z- +b0 [- +b0 \- +b0 ]- +b0 ^- +b0 _- +sHdlNone\x20(0) `- +b0 a- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) b- +b0 c- +b0 d- +b0 e- +b0 f- +b0 g- +b0 h- +b0 i- +b0 j- +b0 k- +b0 l- +b0 m- +b0 n- +b0 o- +b0 p- +b0 q- +b0 r- +b0 s- +b0 t- +b0 u- +b0 v- +b0 w- +b0 x- +b0 y- +b0 z- +b0 {- +b0 |- +b0 }- +b0 ~- +b0 !. +b0 ". +b0 #. +b0 $. +b0 %. +b0 &. +b0 '. +b0 (. +b0 ). +b0 *. +b0 +. +b0 ,. +b0 -. +b0 .. +b0 /. +b0 0. +b0 1. +b0 2. +b0 3. +b0 4. +b0 5. +b0 6. +b0 7. +b0 8. +b0 9. +b0 :. +b0 ;. +b0 <. +b0 =. +b0 >. +b0 ?. +b0 @. +b0 A. +b0 B. +b0 C. +b0 D. +sHdlNone\x20(0) E. +b0 F. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) G. +b0 H. +b0 I. +b0 J. +b0 K. +b0 L. +b0 M. +b0 N. +b0 O. +b0 P. +b0 Q. +b0 R. +b0 S. +b0 T. +b0 U. +b0 V. +b0 W. +b0 X. +b0 Y. +b0 Z. +b0 [. +b0 \. +b0 ]. +b0 ^. +b0 _. +b0 `. +b0 a. +b0 b. +b0 c. +b0 d. +b0 e. +b0 f. +b0 g. +b0 h. +b0 i. +b0 j. +b0 k. +b0 l. +b0 m. +b0 n. +b0 o. +b0 p. +b0 q. +b0 r. +b0 s. +b0 t. +b0 u. +b0 v. +b0 w. +b0 x. +b0 y. +b0 z. +b0 {. +b0 |. +b0 }. +b0 ~. +b0 !/ +b0 "/ +b0 #/ +b0 $/ +b0 %/ +b0 &/ +b0 '/ +b0 (/ +b0 )/ +sHdlNone\x20(0) */ +b0 +/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,/ +0-/ +1./ +sHdlNone\x20(0) // +sRead\x20(0) 0/ +b0 1/ +b0 2/ +b0 3/ +b0 4/ +b0 5/ +b0 6/ +b0 7/ +b0 8/ +b0 9/ +b0 :/ +b0 ;/ +b0 / +b0 ?/ +b0 @/ +b0 A/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) B/ +0C/ +sHdlNone\x20(0) D/ +sSuccess\x20(0) E/ +sRead\x20(0) F/ +sGeneric\x20(0) G/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) X/ +0Y/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z/ +sHdlSome\x20(1) [/ +b1000000000000 \/ +b0 ]/ +0^/ +sHdlNone\x20(0) _/ +b0 `/ +sPhantomConst(\"1..=16\") a/ +0b/ +sHdlNone\x20(0) c/ +b0 d/ +b0 e/ +b0 f/ +b0 g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +b0 p/ +b0 q/ +b0 r/ +b0 s/ +b0 t/ +sPhantomConst(\"0..=16\") u/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v/ +sHdlNone\x20(0) w/ +b0 x/ +b0 y/ +b0 z/ +b0 {/ +b0 |/ +b0 }/ +b0 ~/ +b0 !0 +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b0 &0 +b0 '0 +b0 (0 +b0 )0 +b0 *0 +b0 +0 +sHdlNone\x20(0) ,0 +sGeneric\x20(0) -0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .0 +1/0 +b0 00 +sPhantomConst(\"0..=16\") 10 +b0 20 +030 +040 +b0 50 +b0 60 +b0 70 +b0 80 +b0 90 +b0 :0 +b0 ;0 +b0 <0 +b0 =0 +b0 >0 +b0 ?0 +b0 @0 +b0 A0 +b0 B0 +b0 C0 +b0 D0 +b0 E0 +b0 F0 +b0 G0 +b0 H0 +b0 I0 +b0 J0 +b0 K0 +b0 L0 +b0 M0 +b0 N0 +b0 O0 +b0 P0 +b0 Q0 +b0 R0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +b0 [0 +b0 \0 +b0 ]0 +b0 ^0 +b0 _0 +b0 `0 +b0 a0 +b0 b0 +b0 c0 +b0 d0 +b0 e0 +b0 f0 +b0 g0 +b0 h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +b0 m0 +b0 n0 +b0 o0 +b0 p0 +b0 q0 +b0 r0 +b0 s0 +b0 t0 +sHdlNone\x20(0) u0 +b0 v0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) w0 +0x0 +b0 y0 +b0 z0 +b0 {0 +b0 |0 +b0 }0 +b0 ~0 +b0 !1 +b0 "1 +b0 #1 +b0 $1 +b0 %1 +b0 &1 +b0 '1 +b0 (1 +b0 )1 +b0 *1 +b0 +1 +b0 ,1 +b0 -1 +b0 .1 +b0 /1 +b0 01 +b0 11 +b0 21 +b0 31 +b0 41 +b0 51 +b0 61 +b0 71 +b0 81 +b0 91 +b0 :1 +b0 ;1 +b0 <1 +b0 =1 +b0 >1 +b0 ?1 +b0 @1 +b0 A1 +b0 B1 +b0 C1 +b0 D1 +b0 E1 +b0 F1 +b0 G1 +b0 H1 +b0 I1 +b0 J1 +b0 K1 +b0 L1 +b0 M1 +b0 N1 +b0 O1 +b0 P1 +b0 Q1 +b0 R1 +b0 S1 +b0 T1 +b0 U1 +b0 V1 +b0 W1 +b0 X1 +b0 Y1 +b0 Z1 +sHdlNone\x20(0) [1 +b0 \1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]1 +0^1 +0_1 +0`1 +0a1 +0b1 +0c1 +0d1 +0e1 +0f1 +0g1 +0h1 +0i1 +0j1 +0k1 +0l1 +0m1 +0n1 +0o1 +0p1 +0q1 +0r1 +0s1 +0t1 +0u1 +0v1 +0w1 +0x1 +0y1 +0z1 +0{1 +0|1 +0}1 +0~1 +0!2 +0"2 +0#2 +0$2 +0%2 +0&2 +0'2 +0(2 +0)2 +0*2 +0+2 +0,2 +0-2 +0.2 +0/2 +002 +012 +022 +032 +042 +052 +062 +072 +082 +092 +0:2 +0;2 +0<2 +0=2 +0>2 +0?2 +0@2 +b0 A2 +b0 B2 +sStart\x20(0) C2 +0D2 +sHdlNone\x20(0) E2 +sGeneric\x20(0) F2 +sHdlNone\x20(0) G2 +b0 H2 +sPhantomConst(\"0..4\") I2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J2 +sHdlNone\x20(0) K2 +b0 L2 +sPhantomConst(\"0..4\") M2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) N2 +b0 O2 +b0 P2 +b0 Q2 +b0 R2 +b0 S2 +b0 T2 +b0 U2 +b0 V2 +b0 W2 +b0 X2 +b0 Y2 +b0 Z2 +b0 [2 +b0 \2 +b0 ]2 +b0 ^2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _2 +b0 `2 +b0 a2 +sStart\x20(0) b2 +0c2 +sHdlNone\x20(0) d2 +sGeneric\x20(0) e2 +sHdlNone\x20(0) f2 +b0 g2 +sPhantomConst(\"0..4\") h2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) i2 +sHdlNone\x20(0) j2 +b0 k2 +sPhantomConst(\"0..4\") l2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m2 +b0 n2 +b0 o2 +b0 p2 +b0 q2 +b0 r2 +b0 s2 +b0 t2 +b0 u2 +b0 v2 +b0 w2 +b0 x2 +b0 y2 +b0 z2 +b0 {2 +b0 |2 +b0 }2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~2 +b0 !3 +b0 "3 +sStart\x20(0) #3 +0$3 +sHdlNone\x20(0) %3 +sGeneric\x20(0) &3 +sHdlNone\x20(0) '3 +b0 (3 +sPhantomConst(\"0..4\") )3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) *3 +sHdlNone\x20(0) +3 +b0 ,3 +sPhantomConst(\"0..4\") -3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .3 +b0 /3 +b0 03 +b0 13 +b0 23 +b0 33 +b0 43 +b0 53 +b0 63 +b0 73 +b0 83 +b0 93 +b0 :3 +b0 ;3 +b0 <3 +b0 =3 +b0 >3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?3 +b0 @3 +b0 A3 +sStart\x20(0) B3 +0C3 +sHdlNone\x20(0) D3 +sGeneric\x20(0) E3 +sHdlNone\x20(0) F3 +b0 G3 +sPhantomConst(\"0..4\") H3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) I3 +sHdlNone\x20(0) J3 +b0 K3 +sPhantomConst(\"0..4\") L3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) M3 +b0 N3 +b0 O3 +b0 P3 +b0 Q3 +b0 R3 +b0 S3 +b0 T3 +b0 U3 +b0 V3 +b0 W3 +b0 X3 +b0 Y3 +b0 Z3 +b0 [3 +b0 \3 +b0 ]3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^3 +b0 _3 +b0 `3 +sStart\x20(0) a3 +0b3 +sHdlNone\x20(0) c3 +sGeneric\x20(0) d3 +sHdlNone\x20(0) e3 +b0 f3 +sPhantomConst(\"0..4\") g3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h3 +sHdlNone\x20(0) i3 +b0 j3 +sPhantomConst(\"0..4\") k3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l3 +b0 m3 +b0 n3 +b0 o3 +b0 p3 +b0 q3 +b0 r3 +b0 s3 +b0 t3 +b0 u3 +b0 v3 +b0 w3 +b0 x3 +b0 y3 +b0 z3 +b0 {3 +b0 |3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }3 +b0 ~3 +b0 !4 +sStart\x20(0) "4 +0#4 +sHdlNone\x20(0) $4 +sGeneric\x20(0) %4 +sHdlNone\x20(0) &4 +b0 '4 +sPhantomConst(\"0..4\") (4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )4 +sHdlNone\x20(0) *4 +b0 +4 +sPhantomConst(\"0..4\") ,4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -4 +b0 .4 +b0 /4 +b0 04 +b0 14 +b0 24 +b0 34 +b0 44 +b0 54 +b0 64 +b0 74 +b0 84 +b0 94 +b0 :4 +b0 ;4 +b0 <4 +b0 =4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) >4 +b0 ?4 +b0 @4 +sStart\x20(0) A4 +0B4 +sHdlNone\x20(0) C4 +sGeneric\x20(0) D4 +sHdlNone\x20(0) E4 +b0 F4 +sPhantomConst(\"0..4\") G4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) H4 +sHdlNone\x20(0) I4 +b0 J4 +sPhantomConst(\"0..4\") K4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) L4 +b0 M4 +b0 N4 +b0 O4 +b0 P4 +b0 Q4 +b0 R4 +b0 S4 +b0 T4 +b0 U4 +b0 V4 +b0 W4 +b0 X4 +b0 Y4 +b0 Z4 +b0 [4 +b0 \4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]4 +b0 ^4 +b0 _4 +sStart\x20(0) `4 +0a4 +sHdlNone\x20(0) b4 +sGeneric\x20(0) c4 +sHdlNone\x20(0) d4 +b0 e4 +sPhantomConst(\"0..4\") f4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) g4 +sHdlNone\x20(0) h4 +b0 i4 +sPhantomConst(\"0..4\") j4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) k4 +b0 l4 +b0 m4 +b0 n4 +b0 o4 +b0 p4 +b0 q4 +b0 r4 +b0 s4 +b0 t4 +b0 u4 +b0 v4 +b0 w4 +b0 x4 +b0 y4 +b0 z4 +b0 {4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |4 +b0 }4 +b0 ~4 +sStart\x20(0) !5 +0"5 +sHdlNone\x20(0) #5 +sGeneric\x20(0) $5 +sHdlNone\x20(0) %5 +b0 &5 +sPhantomConst(\"0..4\") '5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (5 +sHdlNone\x20(0) )5 +b0 *5 +sPhantomConst(\"0..4\") +5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,5 +b0 -5 +b0 .5 +b0 /5 +b0 05 +b0 15 +b0 25 +b0 35 +b0 45 +b0 55 +b0 65 +b0 75 +b0 85 +b0 95 +b0 :5 +b0 ;5 +b0 <5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) =5 +b0 >5 +b0 ?5 +sStart\x20(0) @5 +0A5 +sHdlNone\x20(0) B5 +sGeneric\x20(0) C5 +sHdlNone\x20(0) D5 +b0 E5 +sPhantomConst(\"0..4\") F5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) G5 +sHdlNone\x20(0) H5 +b0 I5 +sPhantomConst(\"0..4\") J5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) K5 +b0 L5 +b0 M5 +b0 N5 +b0 O5 +b0 P5 +b0 Q5 +b0 R5 +b0 S5 +b0 T5 +b0 U5 +b0 V5 +b0 W5 +b0 X5 +b0 Y5 +b0 Z5 +b0 [5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \5 +b0 ]5 +b0 ^5 +sStart\x20(0) _5 +0`5 +sHdlNone\x20(0) a5 +sGeneric\x20(0) b5 +sHdlNone\x20(0) c5 +b0 d5 +sPhantomConst(\"0..4\") e5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) f5 +sHdlNone\x20(0) g5 +b0 h5 +sPhantomConst(\"0..4\") i5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) j5 +b0 k5 +b0 l5 +b0 m5 +b0 n5 +b0 o5 +b0 p5 +b0 q5 +b0 r5 +b0 s5 +b0 t5 +b0 u5 +b0 v5 +b0 w5 +b0 x5 +b0 y5 +b0 z5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) {5 +b0 |5 +b0 }5 +sStart\x20(0) ~5 +0!6 +sHdlNone\x20(0) "6 +sGeneric\x20(0) #6 +sHdlNone\x20(0) $6 +b0 %6 +sPhantomConst(\"0..4\") &6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '6 +sHdlNone\x20(0) (6 +b0 )6 +sPhantomConst(\"0..4\") *6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +6 +b0 ,6 +b0 -6 +b0 .6 +b0 /6 +b0 06 +b0 16 +b0 26 +b0 36 +b0 46 +b0 56 +b0 66 +b0 76 +b0 86 +b0 96 +b0 :6 +b0 ;6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) <6 +b0 =6 +b0 >6 +sStart\x20(0) ?6 +0@6 +sHdlNone\x20(0) A6 +sGeneric\x20(0) B6 +sHdlNone\x20(0) C6 +b0 D6 +sPhantomConst(\"0..4\") E6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) F6 +sHdlNone\x20(0) G6 +b0 H6 +sPhantomConst(\"0..4\") I6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J6 +b0 K6 +b0 L6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +b0 U6 +b0 V6 +b0 W6 +b0 X6 +b0 Y6 +b0 Z6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [6 +b0 \6 +b0 ]6 +sStart\x20(0) ^6 +0_6 +sHdlNone\x20(0) `6 +sGeneric\x20(0) a6 +sHdlNone\x20(0) b6 +b0 c6 +sPhantomConst(\"0..4\") d6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) e6 +sHdlNone\x20(0) f6 +b0 g6 +sPhantomConst(\"0..4\") h6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) i6 +b0 j6 +b0 k6 +b0 l6 +b0 m6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +b0 v6 +b0 w6 +b0 x6 +b0 y6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z6 +b0 {6 +b0 |6 +sStart\x20(0) }6 +0~6 +sHdlNone\x20(0) !7 +sGeneric\x20(0) "7 +sHdlNone\x20(0) #7 +b0 $7 +sPhantomConst(\"0..4\") %7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) &7 +sHdlNone\x20(0) '7 +b0 (7 +sPhantomConst(\"0..4\") )7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) *7 +b0 +7 +b0 ,7 +b0 -7 +b0 .7 +b0 /7 +b0 07 +b0 17 +b0 27 +b0 37 +b0 47 +b0 57 +b0 67 +b0 77 +b0 87 +b0 97 +b0 :7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ;7 +b0 <7 +b0 =7 +sStart\x20(0) >7 +0?7 +sHdlNone\x20(0) @7 +sGeneric\x20(0) A7 +sHdlNone\x20(0) B7 +b0 C7 +sPhantomConst(\"0..4\") D7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) E7 +sHdlNone\x20(0) F7 +b0 G7 +sPhantomConst(\"0..4\") H7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) I7 +b0 J7 +b0 K7 +b0 L7 +b0 M7 +b0 N7 +b0 O7 +b0 P7 +b0 Q7 +b0 R7 +b0 S7 +b0 T7 +b0 U7 +b0 V7 +b0 W7 +b0 X7 +b0 Y7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z7 +b0 [7 +sPhantomConst(\"0..=16\") \7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]7 +0^7 +1_7 +sHdlNone\x20(0) `7 +sRead\x20(0) a7 +b0 b7 +b0 c7 +b0 d7 +b0 e7 +b0 f7 +b0 g7 +b0 h7 +b0 i7 +b0 j7 +b0 k7 +b0 l7 +b0 m7 +b0 n7 +b0 o7 +b0 p7 +b0 q7 +b0 r7 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) s7 +0t7 +sHdlNone\x20(0) u7 +sSuccess\x20(0) v7 +sRead\x20(0) w7 +sGeneric\x20(0) x7 +b0 y7 +b0 z7 +b0 {7 +b0 |7 +b0 }7 +b0 ~7 +b0 !8 +b0 "8 +b0 #8 +b0 $8 +b0 %8 +b0 &8 +b0 '8 +b0 (8 +b0 )8 +b0 *8 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +8 +0,8 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -8 +sHdlSome\x20(1) .8 +b1000000000000 /8 +b0 08 +018 +sHdlNone\x20(0) 28 +b0 38 +sPhantomConst(\"1..=16\") 48 +058 +sHdlNone\x20(0) 68 +b0 78 +b0 88 +b0 98 +b0 :8 +b0 ;8 +b0 <8 +b0 =8 +b0 >8 +b0 ?8 +b0 @8 +b0 A8 +b0 B8 +b0 C8 +b0 D8 +b0 E8 +b0 F8 +b0 G8 +sPhantomConst(\"0..=16\") H8 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) I8 +sHdlNone\x20(0) J8 +b0 K8 +b0 L8 +b0 M8 +b0 N8 +b0 O8 +b0 P8 +b0 Q8 +b0 R8 +b0 S8 +b0 T8 +b0 U8 +b0 V8 +b0 W8 +b0 X8 +b0 Y8 +b0 Z8 +b0 [8 +b0 \8 +sHdlNone\x20(0) ]8 +sGeneric\x20(0) ^8 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _8 +1`8 +b0 a8 +sPhantomConst(\"0..=16\") b8 +b0 c8 +0d8 +0e8 +b0 f8 +b0 g8 +b0 h8 +b0 i8 +b0 j8 +b0 k8 +b0 l8 +b0 m8 +b0 n8 +b0 o8 +b0 p8 +b0 q8 +b0 r8 +b0 s8 +b0 t8 +b0 u8 +b0 v8 +b0 w8 +b0 x8 +b0 y8 +b0 z8 +b0 {8 +b0 |8 +b0 }8 +b0 ~8 +b0 !9 +b0 "9 +b0 #9 +b0 $9 +b0 %9 +b0 &9 +b0 '9 +b0 (9 +b0 )9 +b0 *9 +b0 +9 +b0 ,9 +b0 -9 +b0 .9 +b0 /9 +b0 09 +b0 19 +b0 29 +b0 39 +b0 49 +b0 59 +b0 69 +b0 79 +b0 89 +b0 99 +b0 :9 +b0 ;9 +b0 <9 +b0 =9 +b0 >9 +b0 ?9 +b0 @9 +b0 A9 +b0 B9 +b0 C9 +b0 D9 +b0 E9 +b0 F9 +b0 G9 +sHdlNone\x20(0) H9 +b0 I9 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J9 +0K9 +b0 L9 +b0 M9 +b0 N9 +b0 O9 +b0 P9 +b0 Q9 +b0 R9 +b0 S9 +b0 T9 +b0 U9 +b0 V9 +b0 W9 +b0 X9 +b0 Y9 +b0 Z9 +b0 [9 +b0 \9 +b0 ]9 +b0 ^9 +b0 _9 +b0 `9 +b0 a9 +b0 b9 +b0 c9 +b0 d9 +b0 e9 +b0 f9 +b0 g9 +b0 h9 +b0 i9 +b0 j9 +b0 k9 +b0 l9 +b0 m9 +b0 n9 +b0 o9 +b0 p9 +b0 q9 +b0 r9 +b0 s9 +b0 t9 +b0 u9 +b0 v9 +b0 w9 +b0 x9 +b0 y9 +b0 z9 +b0 {9 +b0 |9 +b0 }9 +b0 ~9 +b0 !: +b0 ": +b0 #: +b0 $: +b0 %: +b0 &: +b0 ': +b0 (: +b0 ): +b0 *: +b0 +: +b0 ,: +b0 -: +sHdlNone\x20(0) .: +b0 /: +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 0: +01: +02: +03: +04: +05: +06: +07: +08: +09: +0:: +0;: +0<: +0=: +0>: +0?: +0@: +0A: +0B: +0C: +0D: +0E: +0F: +0G: +0H: +0I: +0J: +0K: +0L: +0M: +0N: +0O: +0P: +0Q: +0R: +0S: +0T: +0U: +0V: +0W: +0X: +0Y: +0Z: +0[: +0\: +0]: +0^: +0_: +0`: +0a: +0b: +0c: +0d: +0e: +0f: +0g: +0h: +0i: +0j: +0k: +0l: +0m: +0n: +0o: +0p: +0q: +b0 r: +b0 s: +sStart\x20(0) t: +0u: +sHdlNone\x20(0) v: +sGeneric\x20(0) w: +sHdlNone\x20(0) x: +b0 y: +sPhantomConst(\"0..4\") z: +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) {: +sHdlNone\x20(0) |: +b0 }: +sPhantomConst(\"0..4\") ~: +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) !; +b0 "; +b0 #; +b0 $; +b0 %; +b0 &; +b0 '; +b0 (; +b0 ); +b0 *; +b0 +; +b0 ,; +b0 -; +b0 .; +b0 /; +b0 0; +b0 1; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 2; +b0 3; +b0 4; +sStart\x20(0) 5; +06; +sHdlNone\x20(0) 7; +sGeneric\x20(0) 8; +sHdlNone\x20(0) 9; +b0 :; +sPhantomConst(\"0..4\") ;; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) <; +sHdlNone\x20(0) =; +b0 >; +sPhantomConst(\"0..4\") ?; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) @; +b0 A; +b0 B; +b0 C; +b0 D; +b0 E; +b0 F; +b0 G; +b0 H; +b0 I; +b0 J; +b0 K; +b0 L; +b0 M; +b0 N; +b0 O; +b0 P; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Q; +b0 R; +b0 S; +sStart\x20(0) T; +0U; +sHdlNone\x20(0) V; +sGeneric\x20(0) W; +sHdlNone\x20(0) X; +b0 Y; +sPhantomConst(\"0..4\") Z; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [; +sHdlNone\x20(0) \; +b0 ]; +sPhantomConst(\"0..4\") ^; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _; +b0 `; +b0 a; +b0 b; +b0 c; +b0 d; +b0 e; +b0 f; +b0 g; +b0 h; +b0 i; +b0 j; +b0 k; +b0 l; +b0 m; +b0 n; +b0 o; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p; +b0 q; +b0 r; +sStart\x20(0) s; +0t; +sHdlNone\x20(0) u; +sGeneric\x20(0) v; +sHdlNone\x20(0) w; +b0 x; +sPhantomConst(\"0..4\") y; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z; +sHdlNone\x20(0) {; +b0 |; +sPhantomConst(\"0..4\") }; +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~; +b0 !< +b0 "< +b0 #< +b0 $< +b0 %< +b0 &< +b0 '< +b0 (< +b0 )< +b0 *< +b0 +< +b0 ,< +b0 -< +b0 .< +b0 /< +b0 0< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 1< +b0 2< +b0 3< +sStart\x20(0) 4< +05< +sHdlNone\x20(0) 6< +sGeneric\x20(0) 7< +sHdlNone\x20(0) 8< +b0 9< +sPhantomConst(\"0..4\") :< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ;< +sHdlNone\x20(0) << +b0 =< +sPhantomConst(\"0..4\") >< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?< +b0 @< +b0 A< +b0 B< +b0 C< +b0 D< +b0 E< +b0 F< +b0 G< +b0 H< +b0 I< +b0 J< +b0 K< +b0 L< +b0 M< +b0 N< +b0 O< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) P< +b0 Q< +b0 R< +sStart\x20(0) S< +0T< +sHdlNone\x20(0) U< +sGeneric\x20(0) V< +sHdlNone\x20(0) W< +b0 X< +sPhantomConst(\"0..4\") Y< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z< +sHdlNone\x20(0) [< +b0 \< +sPhantomConst(\"0..4\") ]< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^< +b0 _< +b0 `< +b0 a< +b0 b< +b0 c< +b0 d< +b0 e< +b0 f< +b0 g< +b0 h< +b0 i< +b0 j< +b0 k< +b0 l< +b0 m< +b0 n< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o< +b0 p< +b0 q< +sStart\x20(0) r< +0s< +sHdlNone\x20(0) t< +sGeneric\x20(0) u< +sHdlNone\x20(0) v< +b0 w< +sPhantomConst(\"0..4\") x< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) y< +sHdlNone\x20(0) z< +b0 {< +sPhantomConst(\"0..4\") |< +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }< +b0 ~< +b0 != +b0 "= +b0 #= +b0 $= +b0 %= +b0 &= +b0 '= +b0 (= +b0 )= +b0 *= +b0 += +b0 ,= +b0 -= +b0 .= +b0 /= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 0= +b0 1= +b0 2= +sStart\x20(0) 3= +04= +sHdlNone\x20(0) 5= +sGeneric\x20(0) 6= +sHdlNone\x20(0) 7= +b0 8= +sPhantomConst(\"0..4\") 9= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) := +sHdlNone\x20(0) ;= +b0 <= +sPhantomConst(\"0..4\") == +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) >= +b0 ?= +b0 @= +b0 A= +b0 B= +b0 C= +b0 D= +b0 E= +b0 F= +b0 G= +b0 H= +b0 I= +b0 J= +b0 K= +b0 L= +b0 M= +b0 N= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) O= +b0 P= +b0 Q= +sStart\x20(0) R= +0S= +sHdlNone\x20(0) T= +sGeneric\x20(0) U= +sHdlNone\x20(0) V= +b0 W= +sPhantomConst(\"0..4\") X= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Y= +sHdlNone\x20(0) Z= +b0 [= +sPhantomConst(\"0..4\") \= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]= +b0 ^= +b0 _= +b0 `= +b0 a= +b0 b= +b0 c= +b0 d= +b0 e= +b0 f= +b0 g= +b0 h= +b0 i= +b0 j= +b0 k= +b0 l= +b0 m= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) n= +b0 o= +b0 p= +sStart\x20(0) q= +0r= +sHdlNone\x20(0) s= +sGeneric\x20(0) t= +sHdlNone\x20(0) u= +b0 v= +sPhantomConst(\"0..4\") w= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) x= +sHdlNone\x20(0) y= +b0 z= +sPhantomConst(\"0..4\") {= +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |= +b0 }= +b0 ~= +b0 !> +b0 "> +b0 #> +b0 $> +b0 %> +b0 &> +b0 '> +b0 (> +b0 )> +b0 *> +b0 +> +b0 ,> +b0 -> +b0 .> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) /> +b0 0> +b0 1> +sStart\x20(0) 2> +03> +sHdlNone\x20(0) 4> +sGeneric\x20(0) 5> +sHdlNone\x20(0) 6> +b0 7> +sPhantomConst(\"0..4\") 8> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 9> +sHdlNone\x20(0) :> +b0 ;> +sPhantomConst(\"0..4\") <> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) => +b0 >> +b0 ?> +b0 @> +b0 A> +b0 B> +b0 C> +b0 D> +b0 E> +b0 F> +b0 G> +b0 H> +b0 I> +b0 J> +b0 K> +b0 L> +b0 M> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) N> +b0 O> +b0 P> +sStart\x20(0) Q> +0R> +sHdlNone\x20(0) S> +sGeneric\x20(0) T> +sHdlNone\x20(0) U> +b0 V> +sPhantomConst(\"0..4\") W> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) X> +sHdlNone\x20(0) Y> +b0 Z> +sPhantomConst(\"0..4\") [> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \> +b0 ]> +b0 ^> +b0 _> +b0 `> +b0 a> +b0 b> +b0 c> +b0 d> +b0 e> +b0 f> +b0 g> +b0 h> +b0 i> +b0 j> +b0 k> +b0 l> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m> +b0 n> +b0 o> +sStart\x20(0) p> +0q> +sHdlNone\x20(0) r> +sGeneric\x20(0) s> +sHdlNone\x20(0) t> +b0 u> +sPhantomConst(\"0..4\") v> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) w> +sHdlNone\x20(0) x> +b0 y> +sPhantomConst(\"0..4\") z> +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) {> +b0 |> +b0 }> +b0 ~> +b0 !? +b0 "? +b0 #? +b0 $? +b0 %? +b0 &? +b0 '? +b0 (? +b0 )? +b0 *? +b0 +? +b0 ,? +b0 -? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .? +b0 /? +b0 0? +sStart\x20(0) 1? +02? +sHdlNone\x20(0) 3? +sGeneric\x20(0) 4? +sHdlNone\x20(0) 5? +b0 6? +sPhantomConst(\"0..4\") 7? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 8? +sHdlNone\x20(0) 9? +b0 :? +sPhantomConst(\"0..4\") ;? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ? +b0 ?? +b0 @? +b0 A? +b0 B? +b0 C? +b0 D? +b0 E? +b0 F? +b0 G? +b0 H? +b0 I? +b0 J? +b0 K? +b0 L? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) M? +b0 N? +b0 O? +sStart\x20(0) P? +0Q? +sHdlNone\x20(0) R? +sGeneric\x20(0) S? +sHdlNone\x20(0) T? +b0 U? +sPhantomConst(\"0..4\") V? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) W? +sHdlNone\x20(0) X? +b0 Y? +sPhantomConst(\"0..4\") Z? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [? +b0 \? +b0 ]? +b0 ^? +b0 _? +b0 `? +b0 a? +b0 b? +b0 c? +b0 d? +b0 e? +b0 f? +b0 g? +b0 h? +b0 i? +b0 j? +b0 k? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l? +b0 m? +b0 n? +sStart\x20(0) o? +0p? +sHdlNone\x20(0) q? +sGeneric\x20(0) r? +sHdlNone\x20(0) s? +b0 t? +sPhantomConst(\"0..4\") u? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v? +sHdlNone\x20(0) w? +b0 x? +sPhantomConst(\"0..4\") y? +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z? +b0 {? +b0 |? +b0 }? +b0 ~? +b0 !@ +b0 "@ +b0 #@ +b0 $@ +b0 %@ +b0 &@ +b0 '@ +b0 (@ +b0 )@ +b0 *@ +b0 +@ +b0 ,@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -@ +b0 .@ +sPhantomConst(\"0..=16\") /@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 0@ +01@ +12@ +sHdlNone\x20(0) 3@ +sRead\x20(0) 4@ +b0 5@ +b0 6@ +b0 7@ +b0 8@ +b0 9@ +b0 :@ +b0 ;@ +b0 <@ +b0 =@ +b0 >@ +b0 ?@ +b0 @@ +b0 A@ +b0 B@ +b0 C@ +b0 D@ +b0 E@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) F@ +0G@ +sHdlNone\x20(0) H@ +sSuccess\x20(0) I@ +sRead\x20(0) J@ +sGeneric\x20(0) K@ +b0 L@ +b0 M@ +b0 N@ +b0 O@ +b0 P@ +b0 Q@ +b0 R@ +b0 S@ +b0 T@ +b0 U@ +b0 V@ +b0 W@ +b0 X@ +b0 Y@ +b0 Z@ +b0 [@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \@ +0]@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^@ +sHdlSome\x20(1) _@ +b1000000000000 `@ +b0 a@ +0b@ +sHdlNone\x20(0) c@ +b0 d@ +sPhantomConst(\"1..=16\") e@ +0f@ +sHdlNone\x20(0) g@ +b0 h@ +b0 i@ +b0 j@ +b0 k@ +b0 l@ +b0 m@ +b0 n@ +b0 o@ +b0 p@ +b0 q@ +b0 r@ +b0 s@ +b0 t@ +b0 u@ +b0 v@ +b0 w@ +b0 x@ +sPhantomConst(\"0..=16\") y@ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z@ +sHdlNone\x20(0) {@ +b0 |@ +b0 }@ +b0 ~@ +b0 !A +b0 "A +b0 #A +b0 $A +b0 %A +b0 &A +b0 'A +b0 (A +b0 )A +b0 *A +b0 +A +b0 ,A +b0 -A +b0 .A +b0 /A +sHdlNone\x20(0) 0A +sGeneric\x20(0) 1A +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 2A +13A +sHdlNone\x20(0) 4A +b0 5A +sPhantomConst(\"1..=16\") 6A +07A +18A +sHdlNone\x20(0) 9A +sRead\x20(0) :A +b0 ;A +b0 A +b0 ?A +b0 @A +b0 AA +b0 BA +b0 CA +b0 DA +b0 EA +b0 FA +b0 GA +b0 HA +b0 IA +b0 JA +b0 KA +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) LA +0MA +sHdlNone\x20(0) NA +sSuccess\x20(0) OA +sRead\x20(0) PA +sGeneric\x20(0) QA +b0 RA +b0 SA +b0 TA +b0 UA +b0 VA +b0 WA +b0 XA +b0 YA +b0 ZA +b0 [A +b0 \A +b0 ]A +b0 ^A +b0 _A +b0 `A +b0 aA +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) bA +0cA +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) dA +sHdlSome\x20(1) eA +b1000000000000 fA +b0 gA +0hA +sHdlNone\x20(0) iA +b0 jA +sPhantomConst(\"1..=16\") kA +0lA +sHdlNone\x20(0) mA +b0 nA +b0 oA +b0 pA +b0 qA +b0 rA +b0 sA +b0 tA +b0 uA +b0 vA +b0 wA +b0 xA +b0 yA +b0 zA +b0 {A +b0 |A +b0 }A +b0 ~A +sPhantomConst(\"0..=16\") !B +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "B +sHdlNone\x20(0) #B +b0 $B +b0 %B +b0 &B +b0 'B +b0 (B +b0 )B +b0 *B +b0 +B +b0 ,B +b0 -B +b0 .B +b0 /B +b0 0B +b0 1B +b0 2B +b0 3B +b0 4B +b0 5B +sHdlNone\x20(0) 6B +sGeneric\x20(0) 7B +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 8B +19B +sHdlNone\x20(0) :B +b0 ;B +sPhantomConst(\"1..=16\") B +sHdlNone\x20(0) ?B +sRead\x20(0) @B +b0 AB +b0 BB +b0 CB +b0 DB +b0 EB +b0 FB +b0 GB +b0 HB +b0 IB +b0 JB +b0 KB +b0 LB +b0 MB +b0 NB +b0 OB +b0 PB +b0 QB +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) RB +0SB +sHdlNone\x20(0) TB +sSuccess\x20(0) UB +sRead\x20(0) VB +sGeneric\x20(0) WB +b0 XB +b0 YB +b0 ZB +b0 [B +b0 \B +b0 ]B +b0 ^B +b0 _B +b0 `B +b0 aB +b0 bB +b0 cB +b0 dB +b0 eB +b0 fB +b0 gB +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) hB +0iB +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jB +b0 kB +b0 lB +b0 mB +b0 nB +b0 oB +b0 pB +b0 qB +b0 rB +b0 sB +b0 tB +b0 uB +b0 vB +b0 wB +b0 xB +b0 yB +b0 zB +b0 {B +b0 |B +b0 }B +b0 ~B +b0 !C +b0 "C +b0 #C +b0 $C +b0 %C +b0 &C +b0 'C +b0 (C +b0 )C +b0 *C +b0 +C +b0 ,C +b0 -C +b0 .C +b0 /C +b0 0C +b0 1C +b0 2C +b0 3C +b0 4C +b0 5C +b0 6C +b0 7C +b0 8C +b0 9C +b0 :C +b0 ;C +b0 C +b0 ?C +b0 @C +b0 AC +b0 BC +b0 CC +b0 DC +b0 EC +b0 FC +b0 GC +b0 HC +b0 IC +b0 JC +b0 KC +b0 LC +b0 MC +sPhantomConst(\"0..=32\") NC +0OC +1PC +sHdlNone\x20(0) QC +sRead\x20(0) RC +b0 SC +b0 TC +b0 UC +b0 VC +b0 WC +b0 XC +b0 YC +b0 ZC +b0 [C +b0 \C +b0 ]C +b0 ^C +b0 _C +b0 `C +b0 aC +b0 bC +b0 cC +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) dC +0eC +sHdlNone\x20(0) fC +sSuccess\x20(0) gC +sRead\x20(0) hC +sGeneric\x20(0) iC +b0 jC +b0 kC +b0 lC +b0 mC +b0 nC +b0 oC +b0 pC +b0 qC +b0 rC +b0 sC +b0 tC +b0 uC +b0 vC +b0 wC +b0 xC +b0 yC +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) zC +0{C +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":4,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":4,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |C +b0 }C +b0 ~C +b0 !D +b0 "D +b0 #D +b0 $D +b0 %D +b0 &D +b0 'D +b0 (D +b0 )D +b0 *D +b0 +D +b0 ,D +b0 -D +b0 .D +b0 /D +b0 0D +b0 1D +b0 2D +b0 3D +b0 4D +b0 5D +b0 6D +b0 7D +b0 8D +b0 9D +b0 :D +b0 ;D +b0 D +b0 ?D +b0 @D +b0 AD +b0 BD +b0 CD +b0 DD +b0 ED +b0 FD +b0 GD +b0 HD +b0 ID +b0 JD +b0 KD +b0 LD +b0 MD +b0 ND +b0 OD +b0 PD +b0 QD +b0 RD +b0 SD +b0 TD +b0 UD +b0 VD +b0 WD +b0 XD +b0 YD +b0 ZD +b0 [D +b0 \D +b0 ]D +b0 ^D +b0 _D +sPhantomConst(\"0..=32\") `D +$end +130 +1x0 +1^1 +1_1 +1`1 +1a1 +1b1 +1c1 +1d1 +1e1 +1f1 +1g1 +1h1 +1i1 +1j1 +1k1 +1l1 +1m1 +1n1 +1o1 +1p1 +1q1 +1r1 +1s1 +1t1 +1u1 +1v1 +1w1 +1x1 +1y1 +1z1 +1{1 +1|1 +1}1 +1~1 +1!2 +1"2 +1#2 +1$2 +1%2 +1&2 +1'2 +1(2 +1)2 +1*2 +1+2 +1,2 +1-2 +1.2 +1/2 +102 +112 +122 +132 +142 +152 +162 +172 +182 +192 +1:2 +1;2 +1<2 +1=2 +1>2 +1?2 +1@2 +1D2 +1c2 +1$3 +1C3 +1b3 +1#4 +1B4 +1a4 +1"5 +1A5 +1`5 +1!6 +1@6 +1_6 +1~6 +1?7 +1d8 +1K9 +11: +12: +13: +14: +15: +16: +17: +18: +19: +1:: +1;: +1<: +1=: +1>: +1?: +1@: +1A: +1B: +1C: +1D: +1E: +1F: +1G: +1H: +1I: +1J: +1K: +1L: +1M: +1N: +1O: +1P: +1Q: +1R: +1S: +1T: +1U: +1V: +1W: +1X: +1Y: +1Z: +1[: +1\: +1]: +1^: +1_: +1`: +1a: +1b: +1c: +1d: +1e: +1f: +1g: +1h: +1i: +1j: +1k: +1l: +1m: +1n: +1o: +1p: +1q: +1u: +16; +1U; +1t; +15< +1T< +1s< +14= +1S= +1r= +13> +1R> +1q> +12? +1Q? +1p? +1o +1u" +1C/ +1t7 +1G@ +1MA +1SB +1eC +#500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1 20 +b1 c8 +b0 20 +b0 c8 +#1000000 +0! +0" +0Y +0Z +0_" +0`" +0-/ +0./ +0^7 +0_7 +01@ +02@ +07A +08A +0=B +0>B +0OC +0PC +#1500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1 20 +b1 c8 +#2000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#2500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b10 20 +b10 c8 +#3000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#3500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b11 20 +b11 c8 +#4000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#4500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b100 20 +b100 c8 +#5000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#5500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b101 20 +b101 c8 +#6000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#6500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b110 20 +b110 c8 +#7000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#7500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b111 20 +b111 c8 +#8000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#8500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000 20 +b1000 c8 +#9000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#9500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1001 20 +b1001 c8 +#10000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#10500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1010 20 +b1010 c8 +#11000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#11500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1011 20 +b1011 c8 +#12000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#12500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1100 20 +b1100 c8 +#13000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#13500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1101 20 +b1101 c8 +#14000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#14500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1110 20 +b1110 c8 +#15000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#15500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1111 20 +b1111 c8 +#16000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#16500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +1& +1* +1," +10" +12# +16# +1^/ +1b/ +118 +158 +1b@ +1f@ +1hA +1lA +#17000000 +0! +0Y +0_" +0-/ +0^7 +01@ +07A +0=B +0OC +#17500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1 00 +b0 20 +0x0 +0^1 +0_1 +0`1 +0a1 +0b1 +0c1 +0d1 +0e1 +0f1 +0g1 +0h1 +0i1 +0j1 +0k1 +0l1 +0m1 +0n1 +0o1 +0p1 +0q1 +0r1 +0s1 +0t1 +0u1 +0v1 +0w1 +0x1 +0y1 +0z1 +0{1 +0|1 +0}1 +0~1 +0!2 +0"2 +0#2 +0$2 +0%2 +0&2 +0'2 +0(2 +0)2 +0*2 +0+2 +0,2 +0-2 +0.2 +0/2 +002 +012 +022 +032 +042 +052 +062 +072 +082 +092 +0:2 +0;2 +0<2 +0=2 +0>2 +0?2 +0@2 +b1000000000000 A2 +sReadingCache\x20(1) C2 +0D2 +b1 [7 +b1 a8 +b0 c8 +0K9 +01: +02: +03: +04: +05: +06: +07: +08: +09: +0:: +0;: +0<: +0=: +0>: +0?: +0@: +0A: +0B: +0C: +0D: +0E: +0F: +0G: +0H: +0I: +0J: +0K: +0L: +0M: +0N: +0O: +0P: +0Q: +0R: +0S: +0T: +0U: +0V: +0W: +0X: +0Y: +0Z: +0[: +0\: +0]: +0^: +0_: +0`: +0a: +0b: +0c: +0d: +0e: +0f: +0g: +0h: +0i: +0j: +0k: +0l: +0m: +0n: +0o: +0p: +0q: +b1000000000000 r: +sReadingCache\x20(1) t: +0u: +b1 .@ +#18000000 +0! +b1000000010000 $ +b1 % +0Y +b1000000010000 *" +b1 +" +0_" +b1000000010000 0# +b1 1# +0-/ +b1000000010000 \/ +b1 ]/ +0^7 +b1000000010000 /8 +b1 08 +01@ +b1000000010000 `@ +b1 a@ +07A +b1000000010000 fA +b1 gA +0=B +0OC +#18500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +sHdlSome\x20(1) [ +b1000000000000 ] +1'" +sHdlSome\x20(1) a" +b1000000000000 c" +1-# +sHdlSome\x20(1) // +b1000000000000 1/ +1Y/ +b10 00 +sCacheMiss\x20(2) C2 +sHdlSome\x20(1) G2 +sHdlSome\x20(1) K2 +b1000000010000 `2 +b1 a2 +sReadingCache\x20(1) b2 +0c2 +b10 [7 +sHdlSome\x20(1) `7 +b1000000000000 b7 +1,8 +b10 a8 +sCacheMiss\x20(2) t: +sHdlSome\x20(1) x: +sHdlSome\x20(1) |: +b1000000010000 3; +b1 4; +sReadingCache\x20(1) 5; +06; +b10 .@ +sHdlSome\x20(1) 3@ +b1000000000000 5@ +1]@ +sHdlSome\x20(1) 9A +b1000000000000 ;A +1cA +sHdlSome\x20(1) ?B +b1000000000000 AB +1iB +sHdlSome\x20(1) QC +b1000000000000 SC +1{C +#19000000 +0! +b1000000100000 $ +b10 % +0Y +b1000000100000 *" +b10 +" +0_" +b1000000100000 0# +b10 1# +0-/ +b1000000100000 \/ +b10 ]/ +0^7 +b1000000100000 /8 +b10 08 +01@ +b1000000100000 `@ +b10 a@ +07A +b1000000100000 fA +b10 gA +0=B +0OC +#19500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000010000 ] +b1000000010000 c" +b1000000010000 1/ +b11 00 +b1 H2 +sCacheMiss\x20(2) b2 +sHdlSome\x20(1) f2 +sHdlSome\x20(1) j2 +b1000000100000 !3 +b10 "3 +sReadingCache\x20(1) #3 +0$3 +b11 [7 +b1000000010000 b7 +b11 a8 +b1 y: +sCacheMiss\x20(2) 5; +sHdlSome\x20(1) 9; +sHdlSome\x20(1) =; +b1000000100000 R; +b10 S; +sReadingCache\x20(1) T; +0U; +b11 .@ +b1000000010000 5@ +b1000000010000 ;A +b1000000010000 AB +b1000000010000 SC +b1000000000000 kB +b100 lB +b1 MC +b1000000000000 }C +b100 ~C +b1 _D +#20000000 +0! +b100000000 $ +b11 % +0Y +b100000000 *" +b11 +" +0_" +b100000000 0# +b11 1# +0-/ +b100000000 \/ +b11 ]/ +0^7 +b100000000 /8 +b11 08 +01@ +b100000000 `@ +b11 a@ +07A +b100000000 fA +b11 gA +0=B +0OC +#20500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000100000 ] +b1000000100000 c" +b1000000100000 1/ +b100 00 +b100 20 +b10 H2 +sCacheMiss\x20(2) #3 +sHdlSome\x20(1) '3 +sHdlSome\x20(1) +3 +b100000000 @3 +b11 A3 +sReadingCache\x20(1) B3 +0C3 +b100 [7 +b1000000100000 b7 +b100 a8 +b100 c8 +b10 y: +sCacheMiss\x20(2) T; +sHdlSome\x20(1) X; +sHdlSome\x20(1) \; +b100000000 q; +b11 r; +sReadingCache\x20(1) s; +0t; +b100 .@ +b1000000100000 5@ +b1000000100000 ;A +b1000000100000 AB +b1000000100000 SC +b11 lB +b1000000010000 mB +b100 nB +b10 MC +b11 ~C +b1000000010000 !D +b100 "D +b10 _D +#21000000 +0! +b10000111100000000 $ +b100 % +0Y +b10000111100000000 *" +b100 +" +0_" +b10000111100000000 0# +b100 1# +0-/ +b10000111100000000 \/ +b100 ]/ +0^7 +b10000111100000000 /8 +b100 08 +01@ +b10000111100000000 `@ +b100 a@ +07A +b10000111100000000 fA +b100 gA +0=B +0OC +#21500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000110000 ] +b1000000110000 c" +b1000000110000 1/ +b101 00 +b1100 20 +b11 H2 +sCacheMiss\x20(2) B3 +sHdlSome\x20(1) F3 +sHdlSome\x20(1) J3 +b10000111100000000 _3 +b100 `3 +sReadingCache\x20(1) a3 +0b3 +b101 [7 +b1000000110000 b7 +b101 a8 +b1100 c8 +b11 y: +sCacheMiss\x20(2) s; +sHdlSome\x20(1) w; +sHdlSome\x20(1) {; +b10000111100000000 2< +b100 3< +sReadingCache\x20(1) 4< +05< +b101 .@ +b1000000110000 5@ +b1000000110000 ;A +b1000000110000 AB +b1000000110000 SC +b10 lB +b11 nB +b1000000100000 oB +b100 pB +b11 MC +b10 ~C +b11 "D +b1000000100000 #D +b100 $D +b11 _D +#22000000 +0! +b10001111100000000 $ +b101 % +0Y +b10001111100000000 *" +b101 +" +0_" +b10001111100000000 0# +b101 1# +0-/ +b10001111100000000 \/ +b101 ]/ +0^7 +b10001111100000000 /8 +b101 08 +01@ +b10001111100000000 `@ +b101 a@ +07A +b10001111100000000 fA +b101 gA +0=B +0OC +#22500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000000000 ] +b1000000000000 c" +b1000000000000 1/ +b110 00 +sHdlNone\x20(0) G2 +b0 H2 +sCacheMiss\x20(2) a3 +sHdlSome\x20(1) e3 +sHdlSome\x20(1) i3 +b10001111100000000 ~3 +b101 !4 +sReadingCache\x20(1) "4 +0#4 +b110 [7 +b1000000000000 b7 +b110 a8 +sHdlNone\x20(0) x: +b0 y: +sCacheMiss\x20(2) 4< +sHdlSome\x20(1) 8< +sHdlSome\x20(1) << +b10001111100000000 Q< +b101 R< +sReadingCache\x20(1) S< +0T< +b110 .@ +b1000000000000 5@ +b1000000000000 ;A +b1000000000000 AB +b1000000000000 SC +b1 lB +b10 nB +b11 pB +b1000000110000 qB +b100 rB +b100 MC +b1 ~C +b10 "D +b11 $D +b1000000110000 %D +b100 &D +b100 _D +#23000000 +0! +b10010111100000000 $ +b110 % +0Y +b10010111100000000 *" +b110 +" +0_" +b10010111100000000 0# +b110 1# +0-/ +b10010111100000000 \/ +b110 ]/ +0^7 +b10010111100000000 /8 +b110 08 +01@ +b10010111100000000 `@ +b110 a@ +07A +b10010111100000000 fA +b110 gA +0=B +0OC +#23500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000010000 ] +b1000000010000 c" +b1000000010000 1/ +b111 00 +b1 g2 +sCacheMiss\x20(2) "4 +sHdlSome\x20(1) &4 +sHdlSome\x20(1) *4 +b10010111100000000 ?4 +b110 @4 +sReadingCache\x20(1) A4 +0B4 +b111 [7 +b1000000010000 b7 +b111 a8 +b1 :; +sCacheMiss\x20(2) S< +sHdlSome\x20(1) W< +sHdlSome\x20(1) [< +b10010111100000000 p< +b110 q< +sReadingCache\x20(1) r< +0s< +b111 .@ +b1000000010000 5@ +b1000000010000 ;A +b1000000010000 AB +b1000000010000 SC +sHdlSome\x20(1) p +b1010100 t +b1100101 u +b1110011 v +b1110100 w +b100000 x +b1100100 y +b1100001 z +b1110100 { +b1100001 | +b101100 } +b100000 ~ +b1110100 !" +b1100101 "" +b1110011 #" +b1110100 $" +b1101001 %" +sHdlSome\x20(1) v" +b1010100 z" +b1100101 {" +b1110011 |" +b1110100 }" +b100000 ~" +b1100100 !# +b1100001 "# +b1110100 ## +b1100001 $# +b101100 %# +b100000 &# +b1110100 '# +b1100101 (# +b1110011 )# +b1110100 *# +b1101001 +# +sHdlSome\x20(1) D/ +b1010100 H/ +b1100101 I/ +b1110011 J/ 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+b1110100 cB +b1100101 dB +b1110011 eB +b1110100 fB +b1101001 gB +b0 lB +b1 nB +b10 pB +b11 rB +b1000000000000 sB +b100 tB +b101 MC +sHdlSome\x20(1) fC +b1010100 jC +b1100101 kC +b1110011 lC +b1110100 mC +b100000 nC +b1100100 oC +b1100001 pC +b1110100 qC +b1100001 rC +b101100 sC +b100000 tC +b1110100 uC +b1100101 vC +b1110011 wC +b1110100 xC +b1101001 yC +b0 ~C +b1 "D +b10 $D +b11 &D +b1000000000000 'D +b100 (D +b101 _D +#24000000 +0! +b10011111100000000 $ +b111 % +0Y +b10011111100000000 *" +b111 +" +0_" +b10011111100000000 0# +b111 1# +0-/ +b10011111100000000 \/ +b111 ]/ +0^7 +b10011111100000000 /8 +b111 08 +01@ +b10011111100000000 `@ +b111 a@ +07A +b10011111100000000 fA +b111 gA +0=B +0OC +#24500000 +1! +1Y +1_" +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000100000 ] +b1000000100000 c" +b1000000100000 1/ +b1000 00 +b0 20 +1x0 +b1010100 y0 +b1100101 z0 +b1110011 {0 +b1110100 |0 +b100000 }0 +b1100100 ~0 +b1100001 !1 +b1110100 "1 +b1100001 #1 +b101100 $1 +b100000 %1 +b1110100 &1 +b1100101 '1 +b1110011 (1 +b1110100 )1 +b1101001 *1 +1^1 +1_1 +1`1 +1a1 +1b1 +1c1 +1d1 +1e1 +1f1 +1g1 +1h1 +1i1 +1j1 +1k1 +1l1 +1m1 +1@2 +b1 L2 +b1010100 O2 +b1100101 P2 +b1110011 Q2 +b1110100 R2 +b100000 S2 +b1100100 T2 +b1100001 U2 +b1110100 V2 +b1100001 W2 +b101100 X2 +b100000 Y2 +b1110100 Z2 +b1100101 [2 +b1110011 \2 +b1110100 ]2 +b1101001 ^2 +b10 g2 +sCacheMiss\x20(2) A4 +sHdlSome\x20(1) E4 +sHdlSome\x20(1) I4 +b10011111100000000 ^4 +b111 _4 +0a4 +b1000 [7 +b1000000100000 b7 +b1000 a8 +b0 c8 +1K9 +b1010100 L9 +b1100101 M9 +b1110011 N9 +b1110100 O9 +b100000 P9 +b1100100 Q9 +b1100001 R9 +b1110100 S9 +b1100001 T9 +b101100 U9 +b100000 V9 +b1110100 W9 +b1100101 X9 +b1110011 Y9 +b1110100 Z9 +b1101001 [9 +11: +12: +13: +14: +15: +16: +17: +18: +19: +1:: +1;: +1<: +1=: +1>: +1?: +1@: +1q: +b1 }: +b1010100 "; +b1100101 #; +b1110011 $; +b1110100 %; +b100000 &; +b1100100 '; +b1100001 (; +b1110100 ); +b1100001 *; +b101100 +; +b100000 ,; +b1110100 -; +b1100101 .; +b1110011 /; +b1110100 0; +b1101001 1; +b10 :; +sCacheMiss\x20(2) r< +sHdlSome\x20(1) v< +sHdlSome\x20(1) z< +b10011111100000000 1= +b111 2= +04= +b1000 .@ +b1000000100000 5@ +b1000000100000 ;A +b1000000100000 AB +b1000000100000 SC +b1101110 t +b1100111 u +b101110 v +b101110 w +b101110 x +b1010 y +b1010100 z +b1100101 { +b1110011 | +b1110100 } +b1010100 !" +b100000 %" +b1101110 z" +b1100111 {" +b101110 |" +b101110 }" +b101110 ~" +b1010 !# +b1010100 "# +b1100101 ## +b1110011 $# +b1110100 %# +b1010100 '# +b100000 +# +b1101110 H/ +b1100111 I/ +b101110 J/ +b101110 K/ +b101110 L/ +b1010 M/ +b1010100 N/ +b1100101 O/ +b1110011 P/ +b1110100 Q/ +b1010100 S/ +b100000 W/ +b1101110 y7 +b1100111 z7 +b101110 {7 +b101110 |7 +b101110 }7 +b1010 ~7 +b1010100 !8 +b1100101 "8 +b1110011 #8 +b1110100 $8 +b1010100 &8 +b100000 *8 +b1101110 L@ +b1100111 M@ +b101110 N@ +b101110 O@ +b101110 P@ +b1010 Q@ +b1010100 R@ +b1100101 S@ +b1110011 T@ +b1110100 U@ +b1010100 W@ +b100000 [@ +b1101110 RA +b1100111 SA +b101110 TA +b101110 UA +b101110 VA +b1010 WA +b1010100 XA +b1100101 YA +b1110011 ZA +b1110100 [A +b1010100 ]A +b100000 aA +b1101110 XB +b1100111 YB +b101110 ZB +b101110 [B +b101110 \B +b1010 ]B +b1010100 ^B +b1100101 _B +b1110011 `B +b1110100 aB +b1010100 cB +b100000 gB +b1000000010000 kB +b1000000100000 mB +b1000000110000 oB +b1000000000000 qB +b1000000010000 sB +b1101110 jC +b1100111 kC +b101110 lC +b101110 mC +b101110 nC +b1010 oC +b1010100 pC +b1100101 qC +b1110011 rC +b1110100 sC +b1010100 uC +b100000 yC +b1000000010000 }C +b1000000100000 !D +b1000000110000 #D +b1000000000000 %D +b1000000010000 'D +#25000000 +0! +b1000000000000 $ +b1000 % +0Y +b1000000000000 *" +b1000 +" +0_" +b1000000000000 0# +b1000 1# +0-/ +b1000000000000 \/ +b1000 ]/ +0^7 +b1000000000000 /8 +b1000 08 +01@ +b1000000000000 `@ +b1000 a@ +07A +b1000000000000 fA +b1000 gA +0=B +0OC +#25500000 +1! +1Y +1_" +b1010100 e# +b1100101 f# +b1110011 g# +b1110100 h# +b100000 i# +b1100100 j# +b1100001 k# +b1110100 l# +b1100001 m# +b101100 n# +b100000 o# +b1110100 p# +b1100101 q# +b1110011 r# +b1110100 s# +b1101001 t# +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000110000 ] +b1000000110000 c" +b1000000110000 1/ +b1001 00 +b0 y0 +b0 z0 +b0 {0 +b0 |0 +b0 }0 +b0 ~0 +b0 !1 +b0 "1 +b0 #1 +b0 $1 +b0 %1 +b0 &1 +b0 '1 +b0 (1 +b0 )1 +b0 *1 +b1101110 +1 +b1100111 ,1 +b101110 -1 +b101110 .1 +b101110 /1 +b1010 01 +b1010100 11 +b1100101 21 +b1110011 31 +b1110100 41 +b100000 51 +b1010100 61 +b1100101 71 +b1110011 81 +b1110100 91 +b100000 :1 +0^1 +0_1 +0`1 +0a1 +0b1 +0c1 +0d1 +0e1 +0f1 +0g1 +0h1 +0i1 +0j1 +0k1 +0l1 +0m1 +1n1 +1o1 +1p1 +1q1 +1r1 +1s1 +1t1 +1u1 +1v1 +1w1 +1x1 +1y1 +1z1 +1{1 +1|1 +1}1 +b10 L2 +b11 g2 +b1000000000000 }4 +b1000 ~4 +0"5 +b1001 [7 +b1000000110000 b7 +b1001 a8 +b0 L9 +b0 M9 +b0 N9 +b0 O9 +b0 P9 +b0 Q9 +b0 R9 +b0 S9 +b0 T9 +b0 U9 +b0 V9 +b0 W9 +b0 X9 +b0 Y9 +b0 Z9 +b0 [9 +b1101110 \9 +b1100111 ]9 +b101110 ^9 +b101110 _9 +b101110 `9 +b1010 a9 +b1010100 b9 +b1100101 c9 +b1110011 d9 +b1110100 e9 +b100000 f9 +b1010100 g9 +b1100101 h9 +b1110011 i9 +b1110100 j9 +b100000 k9 +01: +02: +03: +04: +05: +06: +07: +08: +09: +0:: +0;: +0<: +0=: +0>: +0?: +0@: +1A: +1B: +1C: +1D: +1E: +1F: +1G: +1H: +1I: +1J: +1K: +1L: +1M: +1N: +1O: +1P: +b10 }: +b11 :; +b1000000000000 P= +b1000 Q= +0S= +b1001 .@ +b1000000110000 5@ +b1000000110000 ;A +b1000000110000 AB +b1000000110000 SC +b1010100 t +b1100101 u +b1110011 v +b1110100 w +b100001 x +b1010 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b0 "" +b0 #" +b0 $" +b0 %" +b1010100 z" +b1100101 {" +b1110011 |" +b1110100 }" +b100001 ~" +b1010 "# +b0 ## +b0 $# +b0 %# +b0 &# +b0 '# +b0 (# +b0 )# +b0 *# +b0 +# +b1010100 H/ +b1100101 I/ +b1110011 J/ +b1110100 K/ +b100001 L/ +b1010 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b1010100 y7 +b1100101 z7 +b1110011 {7 +b1110100 |7 +b100001 }7 +b1010 !8 +b0 "8 +b0 #8 +b0 $8 +b0 %8 +b0 &8 +b0 '8 +b0 (8 +b0 )8 +b0 *8 +b1010100 L@ +b1100101 M@ +b1110011 N@ +b1110100 O@ +b100001 P@ +b1010 R@ +b0 S@ +b0 T@ +b0 U@ +b0 V@ +b0 W@ +b0 X@ +b0 Y@ +b0 Z@ +b0 [@ +b1010100 RA +b1100101 SA +b1110011 TA +b1110100 UA +b100001 VA +b1010 XA +b0 YA +b0 ZA +b0 [A +b0 \A +b0 ]A +b0 ^A +b0 _A +b0 `A +b0 aA +b1010100 XB +b1100101 YB +b1110011 ZB +b1110100 [B +b100001 \B +b1010 ^B +b0 _B +b0 `B +b0 aB +b0 bB +b0 cB +b0 dB +b0 eB +b0 fB +b0 gB +b1000000100000 kB +b1000000110000 mB +b1000000000000 oB +b1000000010000 qB +b1000000100000 sB +b1010100 jC +b1100101 kC +b1110011 lC +b1110100 mC +b100001 nC +b1010 pC +b0 qC +b0 rC +b0 sC +b0 tC +b0 uC +b0 vC +b0 wC +b0 xC +b0 yC +b1000000100000 }C +b1000000110000 !D +b1000000000000 #D +b1000000010000 %D +b1000000100000 'D +#26000000 +0! +b1000000010000 $ +b1001 % +0Y +b1000000010000 *" +b1001 +" +0_" +b1000000010000 0# +b1001 1# +0-/ +b1000000010000 \/ +b1001 ]/ +0^7 +b1000000010000 /8 +b1001 08 +01@ +b1000000010000 `@ +b1001 a@ +07A +b1000000010000 fA +b1001 gA +0=B +0OC +#26500000 +1! +1Y +1_" +b1101110 u# +b1100111 v# +b101110 w# +b101110 x# +b101110 y# +b1010 z# +b1010100 {# +b1100101 |# +b1110011 }# +b1110100 ~# +b100000 !$ +b1010100 "$ +b1100101 #$ +b1110011 $$ +b1110100 %$ +b100000 &$ +1-/ +1^7 +11@ +17A +1=B +1OC +b1000000000000 ] +b1000000000000 c" +b1000000000000 1/ +b1010 00 +b0 +1 +b0 ,1 +b0 -1 +b0 .1 +b0 /1 +b0 01 +b0 11 +b0 21 +b0 31 +b0 41 +b0 51 +b0 61 +b0 71 +b0 81 +b0 91 +b0 :1 +b1010100 ;1 +b1100101 <1 +b1110011 =1 +b1110100 >1 +b100001 ?1 +b1010 @1 +b1010 A1 +0n1 +0o1 +0p1 +0q1 +0r1 +0s1 +0t1 +0u1 +0v1 +0w1 +0x1 +0y1 +0z1 +0{1 +0|1 +0}1 +1~1 +1!2 +1"2 +1#2 +1$2 +1%2 +1&2 +1'2 +1(2 +1)2 +1*2 +1+2 +1,2 +1-2 +1.2 +1/2 +b11 L2 +sHdlNone\x20(0) f2 +b0 g2 +b1000000010000 >5 +b1001 ?5 +0A5 +b1010 [7 +b1000000000000 b7 +b1010 a8 +b0 \9 +b0 ]9 +b0 ^9 +b0 _9 +b0 `9 +b0 a9 +b0 b9 +b0 c9 +b0 d9 +b0 e9 +b0 f9 +b0 g9 +b0 h9 +b0 i9 +b0 j9 +b0 k9 +b1010100 l9 +b1100101 m9 +b1110011 n9 +b1110100 o9 +b100001 p9 +b1010 q9 +b1010 r9 +0A: +0B: +0C: +0D: +0E: +0F: +0G: +0H: +0I: +0J: +0K: +0L: +0M: +0N: +0O: +0P: +1Q: +1R: +1S: +1T: +1U: +1V: +1W: +1X: +1Y: +1Z: +1[: +1\: +1]: +1^: +1_: +1`: +b11 }: +sHdlNone\x20(0) 9; +b0 :; +b1000000010000 o= +b1001 p= +0r= +b1010 .@ +b1000000000000 5@ +b1000000000000 ;A +b1000000000000 AB +b1000000000000 SC +sError\x20(1) q +b0 t +b0 u +b0 v +b0 w +b0 x +b0 y +b0 z +sError\x20(1) w" +b0 z" +b0 {" +b0 |" +b0 }" +b0 ~" +b0 !# +b0 "# +sError\x20(1) E/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +sError\x20(1) v7 +b0 y7 +b0 z7 +b0 {7 +b0 |7 +b0 }7 +b0 ~7 +b0 !8 +sError\x20(1) I@ +b0 L@ +b0 M@ +b0 N@ +b0 O@ +b0 P@ +b0 Q@ +b0 R@ +sError\x20(1) OA +b0 RA +b0 SA +b0 TA +b0 UA +b0 VA +b0 WA +b0 XA +sError\x20(1) UB +b0 XB +b0 YB +b0 ZB +b0 [B +b0 \B +b0 ]B +b0 ^B +b1000000110000 kB +b1000000000000 mB +b1000000010000 oB +b1000000100000 qB +b1000000110000 sB +b11101 tB +sError\x20(1) gC +b0 jC +b0 kC +b0 lC +b0 mC +b0 nC +b0 oC +b0 pC +b1000000110000 }C +b1000000000000 !D +b1000000010000 #D +b1000000100000 %D +b1000000110000 'D +b11101 (D +#27000000 +0! +b1000000100000 $ +b1010 % +0Y +b1000000100000 *" +b1010 +" +0_" +b1000000100000 0# +b1010 1# +0-/ +b1000000100000 \/ +b1010 ]/ +0^7 +b1000000100000 /8 +b1010 08 +01@ +b1000000100000 `@ +b1010 a@ +07A +b1000000100000 fA +b1010 gA +0=B +0OC +#27500000 +1! +1Y +1_" +b1010100 '$ +b1100101 ($ +b1110011 )$ +b1110100 *$ +b100001 +$ +b1010 ,$ +b1010 -$ +1-/ +1^7 +11@ +17A +1=B +1OC +sHdlSome\x20(1) ? +b1000000000000 @ +b1010100 B +b1100101 C +b1110011 D +b1110100 E +b100000 F +b1100100 G +b1100001 H +b1110100 I +b1100001 J +b101100 K +b100000 L +b1110100 M +b1100101 N +b1110011 O +b1110100 P +b1101001 Q +sHdlSome\x20(1) R +b1000000010000 ] +sHdlSome\x20(1) E" +b1000000000000 F" +b1010100 H" +b1100101 I" +b1110011 J" +b1110100 K" +b100000 L" +b1100100 M" +b1100001 N" +b1110100 O" +b1100001 P" +b101100 Q" +b100000 R" +b1110100 S" +b1100101 T" +b1110011 U" +b1110100 V" +b1101001 W" +sHdlSome\x20(1) X" +b1000000010000 c" +sHdlSome\x20(1) K# +b1000000000000 L# +b1010100 N# +b1100101 O# +b1110011 P# +b1110100 Q# +b100000 R# +b1100100 S# +b1100001 T# +b1110100 U# +b1100001 V# +b101100 W# +b100000 X# +b1110100 Y# +b1100101 Z# +b1110011 [# +b1110100 \# +b1101001 ]# +sHdlSome\x20(1) ^# +b1000000010000 1/ +sHdlSome\x20(1) w/ +b1000000000000 x/ +b1010100 z/ +b1100101 {/ +b1110011 |/ +b1110100 }/ +b100000 ~/ +b1100100 !0 +b1100001 "0 +b1110100 #0 +b1100001 $0 +b101100 %0 +b100000 &0 +b1110100 '0 +b1100101 (0 +b1110011 )0 +b1110100 *0 +b1101001 +0 +sHdlSome\x20(1) ,0 +b1011 00 +b1100 20 +0x0 +b0 ;1 +b0 <1 +b0 =1 +b0 >1 +b0 ?1 +b0 @1 +b0 A1 +0~1 +0!2 +0"2 +0#2 +0$2 +0%2 +0&2 +0'2 +0(2 +0)2 +0*2 +0+2 +0,2 +0-2 +0.2 +0/2 +0@2 +sReturning\x20(3) C2 +sHdlSome\x20(1) E2 +sHdlNone\x20(0) K2 +b0 L2 +b1 (3 +sReadingCache\x20(1) `4 +b1000000100000 ]5 +b1010 ^5 +0`5 +b1011 [7 +b1000000010000 b7 +sHdlSome\x20(1) J8 +b1000000000000 K8 +b1010100 M8 +b1100101 N8 +b1110011 O8 +b1110100 P8 +b100000 Q8 +b1100100 R8 +b1100001 S8 +b1110100 T8 +b1100001 U8 +b101100 V8 +b100000 W8 +b1110100 X8 +b1100101 Y8 +b1110011 Z8 +b1110100 [8 +b1101001 \8 +sHdlSome\x20(1) ]8 +b1011 a8 +b1100 c8 +0K9 +b0 l9 +b0 m9 +b0 n9 +b0 o9 +b0 p9 +b0 q9 +b0 r9 +0Q: +0R: +0S: +0T: +0U: +0V: +0W: +0X: +0Y: +0Z: +0[: +0\: +0]: +0^: +0_: +0`: +0q: +sReturning\x20(3) t: +sHdlSome\x20(1) v: +sHdlNone\x20(0) |: +b0 }: +b1 Y; +sReadingCache\x20(1) 3= +b1000000100000 0> +b1010 1> +03> +b1011 .@ +b1000000010000 5@ +sHdlSome\x20(1) {@ +b1000000000000 |@ +b1010100 ~@ +b1100101 !A +b1110011 "A +b1110100 #A +b100000 $A +b1100100 %A +b1100001 &A +b1110100 'A +b1100001 (A +b101100 )A +b100000 *A +b1110100 +A +b1100101 ,A +b1110011 -A +b1110100 .A +b1101001 /A +sHdlSome\x20(1) 0A +b1000000010000 ;A +sHdlSome\x20(1) #B +b1000000000000 $B +b1010100 &B +b1100101 'B +b1110011 (B +b1110100 )B +b100000 *B +b1100100 +B +b1100001 ,B +b1110100 -B +b1100001 .B +b101100 /B +b100000 0B +b1110100 1B +b1100101 2B +b1110011 3B +b1110100 4B +b1101001 5B +sHdlSome\x20(1) 6B +b1000000010000 AB +b1000000010000 SC +sSuccess\x20(0) q +b1010100 t +b1100101 u +b1110011 v +b1110100 w +b100000 x +b1100100 y +b1100001 z +b1110100 { +b1100001 | +b101100 } +b100000 ~ +b1110100 !" +b1100101 "" +b1110011 #" +b1110100 $" +b1101001 %" +sSuccess\x20(0) w" +b1010100 z" +b1100101 {" +b1110011 |" +b1110100 }" +b100000 ~" +b1100100 !# +b1100001 "# +b1110100 ## +b1100001 $# +b101100 %# +b100000 &# +b1110100 '# +b1100101 (# +b1110011 )# +b1110100 *# +b1101001 +# +sSuccess\x20(0) E/ +b1010100 H/ +b1100101 I/ +b1110011 J/ +b1110100 K/ +b100000 L/ +b1100100 M/ +b1100001 N/ +b1110100 O/ +b1100001 P/ +b101100 Q/ +b100000 R/ +b1110100 S/ +b1100101 T/ +b1110011 U/ +b1110100 V/ +b1101001 W/ +sSuccess\x20(0) v7 +b1010100 y7 +b1100101 z7 +b1110011 {7 +b1110100 |7 +b100000 }7 +b1100100 ~7 +b1100001 !8 +b1110100 "8 +b1100001 #8 +b101100 $8 +b100000 %8 +b1110100 &8 +b1100101 '8 +b1110011 (8 +b1110100 )8 +b1101001 *8 +sSuccess\x20(0) I@ +b1010100 L@ +b1100101 M@ +b1110011 N@ +b1110100 O@ +b100000 P@ +b1100100 Q@ +b1100001 R@ +b1110100 S@ +b1100001 T@ +b101100 U@ +b100000 V@ +b1110100 W@ +b1100101 X@ +b1110011 Y@ +b1110100 Z@ +b1101001 [@ +sSuccess\x20(0) OA +b1010100 RA +b1100101 SA +b1110011 TA +b1110100 UA +b100000 VA +b1100100 WA +b1100001 XA +b1110100 YA +b1100001 ZA +b101100 [A +b100000 \A +b1110100 ]A +b1100101 ^A +b1110011 _A +b1110100 `A +b1101001 aA +sSuccess\x20(0) UB +b1010100 XB +b1100101 YB +b1110011 ZB +b1110100 [B +b100000 \B +b1100100 ]B +b1100001 ^B +b1110100 _B +b1100001 `B +b101100 aB +b100000 bB +b1110100 cB +b1100101 dB +b1110011 eB +b1110100 fB +b1101001 gB +b1000000000000 kB +b1000000010000 mB +b1000000100000 oB +b1000000110000 qB +b11100 rB +b1000000000000 sB +b100 tB +sSuccess\x20(0) gC +b1010100 jC +b1100101 kC +b1110011 lC +b1110100 mC +b100000 nC +b1100100 oC +b1100001 pC +b1110100 qC +b1100001 rC +b101100 sC +b100000 tC +b1110100 uC +b1100101 vC +b1110011 wC +b1110100 xC +b1101001 yC +b1000000000000 }C +b1000000010000 !D +b1000000100000 #D +b1000000110000 %D +b11100 &D +b1000000000000 'D +b100 (D +#28000000 +0! +b1000000000000 $ +b1011 % +0Y +b1000000000000 *" +b1011 +" +0_" +b1000000000000 0# +b1011 1# +0-/ +b1000000000000 \/ +b1011 ]/ +0^7 +b1000000000000 /8 +b1011 08 +01@ +b1000000000000 `@ +b1011 a@ +07A +b1000000000000 fA +b1011 gA +0=B +0OC +#28500000 diff --git a/crates/cpu/tests/fetch.rs b/crates/cpu/tests/fetch.rs new file mode 100644 index 0000000..fe330a8 --- /dev/null +++ b/crates/cpu/tests/fetch.rs @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use cpu::{ + config::{CpuConfig, UnitConfig}, + fetch::{ + FetchToDecodeInterface, FetchToDecodeInterfaceInner, MemoryInterface, + MemoryOperationErrorKind, MemoryOperationFinish, MemoryOperationFinishKind, + MemoryOperationKind, MemoryOperationStart, fetch, + }, + next_pc::{NextPcToFetchInterface, NextPcToFetchInterfaceInner}, + unit::UnitKind, + util::array_vec::ArrayVec, +}; +use fayalite::{ + prelude::*, + sim::vcd::VcdWriterDecls, + util::{DebugAsDisplay, RcWriter}, +}; +use std::{cell::RefCell, collections::VecDeque, fmt, num::NonZeroUsize}; + +struct Random { + index: u64, +} + +impl Random { + fn next(&mut self) -> u64 { + let index = self.index; + self.index = self.index.wrapping_add(1); + // make a pseudo-random number deterministically based on index + index + .wrapping_add(1) + .wrapping_mul(0x18C49126EABE7A0D) // random prime + .rotate_left(32) + .wrapping_mul(0x92B38C197608A6B) // random prime + .rotate_right(60) + } +} + +const MEMORY_QUEUE_SIZE: usize = 16; + +#[hdl] +struct MemoryQueueEntry { + addr: UInt<64>, + fetch_block_id: UInt<8>, + cycles_left: UInt<8>, +} + +impl MemoryQueueEntry { + #[hdl] + fn default_sim(self) -> SimValue { + #[hdl(sim)] + Self { + addr: 0u64, + fetch_block_id: 0u8, + cycles_left: 0u8, + } + } + fn get_next_delay(random: &mut Random) -> u8 { + if random.next() % 32 == 0 { 30 } else { 5 } + } +} + +const MEMORY_DATA: &str = "Test data, testing...\nTest Test!\nSecond Cache Line\nTesting.....\n"; +const MEMORY_START: u64 = 0x1000; +const MEMORY_RANGE2: std::ops::Range = 0x2000..0x3000; +const MEMORY_ERROR_RANGE: std::ops::Range = 0x10F00..0x20F00; +const MEMORY_ERROR_STEP: u64 = 0x1000; + +fn read_memory(start: u64, len: usize) -> Option<&'static [u8]> { + if MEMORY_ERROR_RANGE.contains(&start) { + let start = start - MEMORY_ERROR_RANGE.start; + let index = start / MEMORY_ERROR_STEP; + let offset = start % MEMORY_ERROR_STEP; + return if index < offset { + [0xFFu8; MEMORY_DATA.len()].get(..len) + } else { + None + }; + } + if MEMORY_RANGE2.contains(&start) { + return [0xF2u8; MEMORY_DATA.len()].get(..len); + } + MEMORY_DATA + .as_bytes() + .get(start.checked_sub(MEMORY_START)?.try_into().ok()?..)? + .get(..len) +} + +#[hdl_module(extern)] +fn mock_memory(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.input(MemoryInterface[config]); + #[hdl] + let queue_debug: ArrayVec> = m.output(); + m.register_clock_for_past(cd.clk); + m.extern_module_simulation_fn( + (cd, memory_interface, queue_debug), + |(cd, memory_interface, queue_debug), mut sim| async move { + // intentionally have a different sequence each time we're reset + let random = RefCell::new(Random { index: 0 }); + sim.resettable( + cd, + async |mut sim| { + sim.write(memory_interface.start.ready, false).await; + sim.write( + memory_interface.finish.data, + memory_interface.ty().finish.data.HdlNone(), + ) + .await; + sim.write( + queue_debug, + queue_debug.ty().new_sim(MemoryQueueEntry.default_sim()), + ) + .await; + }, + |sim, ()| run_fn(cd, memory_interface, queue_debug, &random, sim), + ) + .await; + }, + ); + #[hdl] + async fn run_fn( + cd: Expr, + memory_interface: Expr>>, + queue_debug: Expr>>, + random: &RefCell, + mut sim: ExternModuleSimulationState, + ) { + let mut random = random.borrow_mut(); + let config = memory_interface.config.ty(); + let finish_data_ty = memory_interface.finish.data.ty(); + let mut queue: VecDeque> = VecDeque::new(); + loop { + for entry in &mut queue { + entry.cycles_left = entry.cycles_left.as_int().saturating_sub(1).to_sim_value(); + } + let sim_queue = queue_debug + .ty() + .from_iter_sim(MemoryQueueEntry.default_sim(), &queue) + .ok() + .expect("queue is known to be small enough"); + sim.write(queue_debug, sim_queue).await; + sim.write_bool( + memory_interface.start.ready, + queue.len() < MEMORY_QUEUE_SIZE && random.next() % 32 != 0, + ) + .await; + let finish_data = if let Some(entry) = queue + .front() + .filter(|entry| entry.cycles_left.as_int() == 0) + { + #[hdl(sim)] + let MemoryQueueEntry { + addr, + fetch_block_id: _, + cycles_left: _, + } = entry; + let addr = addr.as_int(); + let mut read_data = + repeat(0u8, finish_data_ty.HdlSome.read_data.len()).to_sim_value(); + let kind = if let Some(data) = read_memory(addr, read_data.len()) { + for (l, r) in read_data.iter_mut().zip(data) { + *l = r.to_sim_value(); + } + #[hdl(sim)] + MemoryOperationFinishKind.Success( + #[hdl(sim)] + MemoryOperationKind.Read(), + ) + } else { + #[hdl(sim)] + MemoryOperationFinishKind.Error( + #[hdl(sim)] + MemoryOperationErrorKind.Generic(), + ) + }; + #[hdl(sim)] + finish_data_ty.HdlSome( + #[hdl(sim)] + MemoryOperationFinish::<_> { + kind, + read_data, + config, + }, + ) + } else { + #[hdl(sim)] + finish_data_ty.HdlNone() + }; + sim.write(memory_interface.finish.data, &finish_data).await; + sim.wait_for_clock_edge(cd.clk).await; + println!( + "Dump mock memory queue: {:#?}", + Vec::from_iter(queue.iter().map(|v| { + DebugAsDisplay(format!( + "fid={:#x} addr={:#x}", + v.fetch_block_id.as_int(), + v.addr.as_int(), + )) + })) + ); + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(memory_operation_start) = + sim.read_past(memory_interface.start.data, cd.clk).await + { + #[hdl(sim)] + let MemoryOperationStart::<_> { + kind, + addr, + write_data: _, + fetch_block_id, + config: _, + } = memory_operation_start; + #[hdl(sim)] + match kind { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + let entry = #[hdl(sim)] + MemoryQueueEntry { + addr, + fetch_block_id, + cycles_left: MemoryQueueEntry::get_next_delay(&mut random), + }; + println!("mock memory start: {entry:#?}"); + queue.push_back(entry); + } + } + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(finish_data) = finish_data { + let Some(entry) = queue.pop_front() else { + unreachable!(); + }; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = finish_data; + let kind = #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Error(_) => Err(()), + MemoryOperationFinishKind::Success(_) => Ok(()), + }; + println!( + "mock memory finish: kind={kind:?} read_data={read_data:?} {entry:#?}" + ); + } + } + } + } +} + +#[hdl_module] +fn dut(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let fetch = instance(fetch(config)); + #[hdl] + let fetch { + cd: fetch_cd, + memory_interface: fetch_memory_interface, + from_next_pc: fetch_from_next_pc, + to_decode: fetch_to_decode, + } = fetch; + connect(fetch_cd, cd); + connect(fetch_from_next_pc, from_next_pc); + connect(to_decode, fetch_to_decode); + #[hdl] + let mock_memory = instance(mock_memory(config)); + #[hdl] + let mock_memory { + cd: mock_memory_cd, + memory_interface: mock_memory_interface, + queue_debug: _, + } = mock_memory; + connect(mock_memory_cd, cd); + connect(mock_memory_interface, fetch_memory_interface); +} + +#[derive(Clone)] +struct FetchTestOperation { + start_pc: u64, + fetch_block_id: u8, + fetch_block_data: [u8; FETCH_WIDTH_IN_BYTES], + error: Option>, +} + +impl PartialEq for FetchTestOperation { + #[hdl] + fn eq(&self, other: &Self) -> bool { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + ref error, + } = *self; + if let Some(error) = error { + #[hdl(sim)] + match error { + MemoryOperationErrorKind::Generic => {} + } + } + start_pc == other.start_pc + && fetch_block_id == other.fetch_block_id + && fetch_block_data == other.fetch_block_data + && error.is_some() == other.error.is_some() + } +} + +impl fmt::Debug for FetchTestOperation { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + error, + } = self; + let mut debug_struct = f.debug_struct("FetchTestOperation"); + debug_struct.field("start_pc", &format_args!("{start_pc:#x}")); + debug_struct.field("fetch_block_id", &format_args!("{fetch_block_id:#x}")); + if fetch_block_data.iter().all(|v| *v == fetch_block_data[0]) { + debug_struct.field( + "fetch_block_data", + &format_args!( + "[b'{}'; {FETCH_WIDTH_IN_BYTES}]", + fetch_block_data[0].escape_ascii(), + ), + ); + } else { + debug_struct.field( + "fetch_block_data", + &format_args!("b\"{}\"", fetch_block_data.escape_ascii()), + ); + } + debug_struct.field("error", error).finish() + } +} + +const LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; +const FETCH_WIDTH_IN_BYTES: usize = 1 << LOG2_FETCH_WIDTH_IN_BYTES; +const LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 5; +const CACHE_LINE_SIZE_IN_BYTES: usize = 1 << LOG2_CACHE_LINE_SIZE_IN_BYTES; + +// needs to be a multiple of the cache line size +const _: [(); CACHE_LINE_SIZE_IN_BYTES * 2] = [(); MEMORY_DATA.len()]; + +fn fetch_test_operations() -> Vec { + #[track_caller] + fn mem_data(r: std::ops::RangeFrom) -> [u8; FETCH_WIDTH_IN_BYTES] { + *MEMORY_DATA[r] + .as_bytes() + .first_chunk() + .expect("start should be in-range") + } + #[hdl] + fn generic_error() -> SimValue { + #[hdl(sim)] + MemoryOperationErrorKind.Generic() + } + let mut last_fetch_block_id = 0u8.wrapping_sub(1); + macro_rules! op { + { + $($field:ident: $value:expr,)* + } => { + FetchTestOperation { + fetch_block_id: { + last_fetch_block_id = last_fetch_block_id.wrapping_add(1); + last_fetch_block_id + }, + $($field: $value,)* + } + }; + } + vec![ + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x100, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 2, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 3, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + ] +} + +#[test] +#[hdl] +fn test_fetch() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut config = CpuConfig::new( + vec![ + UnitConfig::new(UnitKind::AluBranch), + UnitConfig::new(UnitKind::AluBranch), + ], + NonZeroUsize::new(20).unwrap(), + ); + config.fetch_width = NonZeroUsize::new(2).unwrap(); + config.log2_fetch_width_in_bytes = LOG2_FETCH_WIDTH_IN_BYTES; + config.log2_cache_line_size_in_bytes = LOG2_CACHE_LINE_SIZE_IN_BYTES; + config.log2_l1_i_cache_line_count = 4; + let m = dut(PhantomConst::new_sized(config)); + let mut sim = Simulation::new(m); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + let from_next_pc_ty = sim.io().from_next_pc.ty(); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + sim.write( + sim.io().from_next_pc.cancel.data, + from_next_pc_ty.cancel.data.HdlNone(), + ); + sim.write( + sim.io().from_next_pc.fetch.data, + from_next_pc_ty.fetch.data.HdlNone(), + ); + sim.write(sim.io().to_decode.fetched.ready, true); + let operations = fetch_test_operations(); + let mut started_operations = 0; + let mut finished_operations = 0; + for cycle in 0..200 { + sim.write( + sim.io().from_next_pc.fetch.data, + if let Some(op) = operations.get(started_operations) { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + NextPcToFetchInterfaceInner { + start_pc: op.start_pc, + fetch_block_id: op.fetch_block_id, + }, + ) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.advance_time(SimDuration::from_nanos(500)); + if sim.read_bool(sim.io().from_next_pc.fetch.ready) { + #[hdl(sim)] + if let HdlSome(_) = sim.read(sim.io().from_next_pc.fetch.data) { + println!("started fetch: {:#?}", operations[started_operations]); + started_operations += 1; + } + } + if sim.read_bool(sim.io().to_decode.fetched.ready) { + #[hdl(sim)] + if let HdlSome(fetched) = sim.read(sim.io().to_decode.fetched.data) { + #[hdl(sim)] + let FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config: _, + } = &fetched; + let Some(expected_op) = operations.get(finished_operations) else { + panic!("too many finished operations: {fetched:#?}"); + }; + let op = FetchTestOperation { + start_pc: start_pc.as_int(), + fetch_block_id: fetch_block_id.as_int(), + error: #[hdl(sim)] + match error { + HdlSome(e) => Some(e.clone()), + HdlNone => None, + }, + fetch_block_data: std::array::from_fn(|i| fetch_block_data[i].as_int()), + }; + println!("finished fetch: op={op:#?}"); + assert_eq!( + op, *expected_op, + "cycle={cycle} finished_operations={finished_operations}", + ); + finished_operations += 1; + } + } + println!("clock tick: {cycle}"); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + assert_eq!(finished_operations, operations.len()); + // FIXME: vcd is just whatever fetch does now, which isn't known to be correct + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("expected/fetch.vcd") { + panic!(); + } +}