programmerjake/cpu
1
0
Fork 0
forked from libre-chip/cpu
Code Pull requests Activity

UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming

Browse source
This commit is contained in:
Jacob Lifshay 2025-02-28 17:45:46 -08:00
parent 6c91d1b0b0
commit 518284685f
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
6 changed files with 33960 additions and 32521 deletions
Download patch file Download diff file Expand all files Collapse all files

54
crates/cpu/src/reg_alloc.rs
View file

@ -3,13 +3,13 @@
use crate::{
config::CpuConfig,
instruction::{
MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, RenameTableName, UnitOutRegNum,
MOp, MOpDestReg, MOpRegNum, MOpTrait, MoveRegMOp, PRegNum, RenameTableName, UnitOutRegNum,
COMMON_MOP_SRC_LEN,
},
unit::{
unit_base::{UnitForwardingInfo, UnitInput},
GlobalState, TrapData, UnitOutput, UnitOutputWrite, UnitResult, UnitResultCompleted,
UnitTrait,
GlobalState, TrapData, UnitMOp, UnitOutput, UnitOutputWrite, UnitResult,
UnitResultCompleted, UnitTrait,
},
util::tree_reduce::tree_reduce_with_state,
};
@ -234,7 +234,7 @@ pub fn reg_alloc(config: &CpuConfig) {
wire(Array[HdlOption[UInt[config.unit_num_width()]]][config.fetch_width.get()]);
#[hdl]
let renamed_mops =
wire(Array[HdlOption[UnitInput[config.unit_mop_in_unit()]]][config.fetch_width.get()]);
wire(Array[HdlOption[UnitInput[config.renamed_mop_in_unit()]]][config.fetch_width.get()]);
#[hdl]
let renamed_mops_out_reg = wire(Array[HdlOption[config.p_reg_num()]][config.fetch_width.get()]);
for fetch_index in 0..config.fetch_width.get() {
@ -358,27 +358,35 @@ pub fn reg_alloc(config: &CpuConfig) {
#[hdl]
if let HdlSome(renamed_mop_out_reg) = renamed_mops_out_reg[fetch_index] {
let dest_reg = MOpTrait::dest_reg(decoded_insn.mop);
connect(
renamed_mops[fetch_index],
HdlSome(
#[hdl]
UnitInput::<_> {
mop: MOpTrait::map_regs(
decoded_insn.mop,
renamed_mop_out_reg.unit_out_reg,
config.p_reg_num_width(),
&mut |src_reg, src_index| {
connect(
rename_table_read_ports[src_index].addr,
#[hdl]
MOpRegNum { value: src_reg },
);
rename_table_read_ports[src_index].data.cast_to_bits()
},
),
pc: decoded_insn.pc,
let renamed_mop = UnitMOp::try_with_transformed_move_op(
MOpTrait::map_regs(
decoded_insn.mop,
renamed_mop_out_reg.unit_out_reg,
config.p_reg_num_width(),
&mut |src_reg, src_index| {
connect(
rename_table_read_ports[src_index].addr,
#[hdl]
MOpRegNum { value: src_reg },
);
rename_table_read_ports[src_index].data.cast_to_bits()
},
),
config.renamed_mop_in_unit().TransformedMove,
|renamed_mop, renamed_move_op: Expr<MoveRegMOp<_, _>>| {
// TODO: finish handling MoveRegMOp
connect(renamed_mop, Expr::ty(renamed_mop).HdlNone());
},
);
connect(
renamed_mops[fetch_index],
HdlOption::map(renamed_mop, |mop| {
#[hdl]
UnitInput::<_> {
mop,
pc: decoded_insn.pc,
}
}),
);
for (reg, reg_kind) in MOpDestReg::regs(dest_reg)
.into_iter()