add MemoryOperationStart.rw_mask

crates/cpu/src/fetch.rs

@@ -452,6 +452,7 @@ impl<C: PhantomConstCpuConfig> L1ICacheStateSim<C> {
                         mem_op_ty.write_data.element().zero(),
                         mem_op_ty.write_data.len(),
                     ),
+                    rw_mask: repeat(true, mem_op_ty.write_data.len()),
                     fetch_block_id,
                     config,
                 },

crates/cpu/src/main_memory_and_io.rs

@@ -21,6 +21,7 @@ pub struct MemoryOperationStart<C: PhantomConstGet<CpuConfig> + PhantomConstCpuC
     pub kind: MemoryOperationKind,
     pub addr: UInt<64>,
     pub write_data: ArrayType<UInt<8>, CpuConfigFetchWidthInBytes<C>>,
+    pub rw_mask: ArrayType<Bool, CpuConfigFetchWidthInBytes<C>>,
     pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, // for debugging
     pub config: C,
 }

crates/cpu/tests/fetch.rs

@@ -234,6 +234,7 @@ fn mock_memory(config: PhantomConst<CpuConfig>) {
                         kind,
                         addr,
                         write_data: _,
+                        rw_mask,
                         fetch_block_id,
                         config: _,
                     } = memory_operation_start;
@@ -242,6 +243,10 @@ fn mock_memory(config: PhantomConst<CpuConfig>) {
                         MemoryOperationKind::Read => {}
                         MemoryOperationKind::Write => unreachable!(),
                     }
+                    assert!(
+                        rw_mask.iter().all(|v| **v),
+                        "rw_mask should be all true: {rw_mask:?}"
+                    );
                     let entry = #[hdl(sim)]
                     MemoryQueueEntry {
                         addr,