programmerjake/cpu
1
0
Fork 0
forked from libre-chip/cpu
Code Pull requests Activity

WIP implementing unit_base

Browse source
This commit is contained in:
Jacob Lifshay 2025-02-19 23:54:41 -08:00
parent ece788dda3
commit 3f6e5cc600
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
10 changed files with 17918 additions and 8115 deletions
Download patch file Download diff file Expand all files Collapse all files

19
crates/cpu/src/reg_alloc.rs
View file

@ -311,7 +311,7 @@ pub fn reg_alloc(config: &CpuConfig) {
SourceLocation::caller(),
);
connect(dyn_unit.cd(unit), cd);
let unit_input_insn = dyn_unit.input_insn(unit);
let unit_to_reg_alloc = dyn_unit.unit_to_reg_alloc(unit);
// TODO: handle assigning multiple instructions to a unit at a time
let assign_to_unit_at_once = NonZeroUsize::new(1).unwrap();
// TODO: handle retiring multiple instructions from a unit at a time
@ -333,8 +333,8 @@ pub fn reg_alloc(config: &CpuConfig) {
);
connect(unit_free_regs_tracker.alloc_out[0].ready, false);
connect(
unit_input_insn.data,
Expr::ty(unit_input_insn).data.HdlNone(),
unit_to_reg_alloc.input_insn.data,
Expr::ty(unit_to_reg_alloc.input_insn).data.HdlNone(),
);
for fetch_index in 0..config.fetch_width.get() {
#[hdl]
@ -343,7 +343,7 @@ pub fn reg_alloc(config: &CpuConfig) {
connect(available_units[fetch_index][unit_index], false);
}
#[hdl]
if !unit_input_insn.ready {
if !unit_to_reg_alloc.input_insn.ready {
// must come after to override connects in loops above
connect(available_units[fetch_index][unit_index], false);
}
@ -356,11 +356,11 @@ pub fn reg_alloc(config: &CpuConfig) {
if let HdlSome(renamed_mop) =
HdlOption::and_then(renamed_mops[fetch_index], |v| dyn_unit.extract_mop(v))
{
connect(unit_input_insn.data, HdlSome(renamed_mop));
connect(unit_to_reg_alloc.input_insn.data, HdlSome(renamed_mop));
} else {
connect(
unit_input_insn.data,
HdlSome(Expr::ty(unit_input_insn).data.HdlSome.uninit()),
unit_to_reg_alloc.input_insn.data,
HdlSome(Expr::ty(unit_to_reg_alloc.input_insn).data.HdlSome.uninit()),
);
// FIXME: add hdl_assert(cd.clk, false.to_expr(), "");
}
@ -387,7 +387,7 @@ pub fn reg_alloc(config: &CpuConfig) {
}
// TODO: connect outputs to other units
connect(
dyn_unit.unit_forwarding_info(unit),
unit_to_reg_alloc.unit_forwarding_info,
#[hdl]
UnitForwardingInfo::<_, _, _> {
unit_output_writes: repeat(
@ -397,10 +397,9 @@ pub fn reg_alloc(config: &CpuConfig) {
_phantom: PhantomData,
},
);
connect(dyn_unit.output(unit).ready, false);
// TODO: handle cancellation
connect(
dyn_unit.cancel_input(unit).data,
unit_to_reg_alloc.cancel_input,
HdlOption[config.unit_cancel_input()].HdlNone(),
);
}