forked from libre-chip/cpu
WIP: adding memory_interface_adapter_no_split
This commit is contained in:
parent
3080ea4ce2
commit
2457116fc0
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
5 changed files with 8841 additions and 13 deletions
File diff suppressed because it is too large
Load diff
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@ -358,9 +358,9 @@ pub fn receiver(queue_capacity: NonZeroUsize) {
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pub const SIMPLE_UART_RECEIVE_OFFSET: u64 = 0;
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pub const SIMPLE_UART_TRANSMIT_OFFSET: u64 = 0;
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pub const SIMPLE_UART_STATUS_OFFSET: u64 = 1;
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pub const SIMPLE_UART_SIZE: NonZeroU64 =
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NonZeroU64::new(1 << SIMPLE_UART_LOG2_SIZE).expect("known to be non-zero");
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pub const SIMPLE_UART_LOG2_SIZE: u8 = 1;
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pub const SIMPLE_UART_LOG2_BUS_WIDTH: u8 = 1;
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pub const SIMPLE_UART_USED_SIZE: NonZeroU64 = NonZeroU64::new(2).expect("known non-zero");
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pub const SIMPLE_UART_ADDRESS_SIZE: NonZeroU64 = NonZeroU64::new(1 << 6).expect("known non-zero");
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#[hdl(no_static)]
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struct Operation<C: PhantomConstGet<MemoryInterfaceConfig>> {
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@ -373,16 +373,18 @@ pub const fn simple_uart_memory_interface_config(
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start_address: Wrapping<u64>,
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) -> MemoryInterfaceConfig {
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assert!(
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start_address.0 % SIMPLE_UART_SIZE.get() == 0,
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start_address
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.0
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.is_multiple_of(SIMPLE_UART_ADDRESS_SIZE.get()),
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"start_address must be properly aligned"
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);
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MemoryInterfaceConfig {
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log2_bus_width_in_bytes: SIMPLE_UART_LOG2_SIZE,
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log2_bus_width_in_bytes: SIMPLE_UART_LOG2_BUS_WIDTH,
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queue_capacity: const { NonZeroUsize::new(1).unwrap() },
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op_id_width,
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address_range: AddressRange::Limited {
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start: start_address,
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size: SIMPLE_UART_SIZE,
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size: SIMPLE_UART_ADDRESS_SIZE,
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},
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}
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}
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7184
crates/cpu/tests/expected/memory_interface_adapter_no_split.vcd
generated
Normal file
7184
crates/cpu/tests/expected/memory_interface_adapter_no_split.vcd
generated
Normal file
File diff suppressed because it is too large
Load diff
660
crates/cpu/tests/memory_interface.rs
Normal file
660
crates/cpu/tests/memory_interface.rs
Normal file
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@ -0,0 +1,660 @@
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use cpu::{
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main_memory_and_io::{
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AddressRange, MemoryInterface, MemoryInterfaceConfig, MemoryOperationErrorKind,
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MemoryOperationFinish, MemoryOperationFinishKind, MemoryOperationKind,
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MemoryOperationStart, memory_interface_adapter_no_split,
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},
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next_pc::FETCH_BLOCK_ID_WIDTH,
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};
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use fayalite::{
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bundle::{BundleField, BundleType},
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intern::{Intern, Interned},
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module::instance_with_loc,
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prelude::*,
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sim::vcd::VcdWriterDecls,
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util::RcWriter,
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};
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use std::{cell::Cell, collections::VecDeque, fmt};
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fn get_next_delay(delay_sequence_index: &Cell<u64>) -> u8 {
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let index = delay_sequence_index.get();
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delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1));
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// make a pseudo-random number deterministically based on index
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let random = index
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.wrapping_add(1)
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.wrapping_mul(0x8c16a62518f86883) // random prime
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.rotate_left(32)
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.wrapping_mul(0xf807b7df2082353d) // random prime
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.rotate_right(60);
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const DELAYS: &[u8; 0x20] = &[
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0, 0, 0, 0, 0, 0, 0, 0, //
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1, 1, 1, 1, 1, 1, 1, 1, //
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2, 2, 2, 2, 2, 2, 2, 2, //
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3, 3, 3, 3, 4, 5, 6, 20, //
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];
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DELAYS[(random & 0x1F) as usize]
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}
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#[hdl_module(extern)]
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fn mock_memory(memory: Memory) {
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let Memory { config, contents } = memory;
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let input_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
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m.input(MemoryInterface[config]);
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m.register_clock_for_past(cd.clk);
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#[hdl]
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async fn run(
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cd: Expr<ClockDomain>,
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input_interface: Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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config: PhantomConst<MemoryInterfaceConfig>,
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contents: Interned<str>,
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delay_sequence_index: &Cell<u64>,
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mut sim: ExternModuleSimulationState,
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) {
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#[derive(Debug)]
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struct Op {
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cycles_left: u8,
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op_id: SimValue<UInt>,
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finish: SimValue<MemoryOperationFinish<PhantomConst<MemoryInterfaceConfig>>>,
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}
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let mut ops = VecDeque::<Op>::with_capacity(config.get().queue_capacity.get());
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let finish_ty = input_interface.ty().finish.data.HdlSome;
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loop {
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for op in &mut ops {
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op.cycles_left = op.cycles_left.saturating_sub(1);
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}
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let next_op_ids_ty = input_interface.ty().next_op_ids.HdlSome;
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sim.write(
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input_interface.next_op_ids,
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#[hdl(sim)]
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(input_interface.ty().next_op_ids).HdlSome(
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next_op_ids_ty
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.from_iter_sim(
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next_op_ids_ty.element().zero(),
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ops.iter().map(|op| &op.op_id),
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)
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.expect("known to fit"),
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),
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)
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.await;
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if let Some(Op {
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cycles_left: 0,
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op_id: _,
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finish,
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}) = ops.front()
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{
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sim.write(
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input_interface.finish.data,
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#[hdl(sim)]
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(input_interface.ty().finish.data).HdlSome(finish),
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)
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.await;
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}
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sim.write_bool(
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input_interface.start.ready,
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ops.len() < config.get().queue_capacity.get(),
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)
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.await;
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sim.wait_for_clock_edge(cd.clk).await;
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if sim
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.read_past_bool(input_interface.finish.ready, cd.clk)
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.await
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{
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ops.pop_front_if(|op| op.cycles_left == 0);
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}
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if sim
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.read_past_bool(input_interface.start.ready, cd.clk)
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.await
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{
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#[hdl(sim)]
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if let HdlSome(start) = sim.read_past(input_interface.start.data, cd.clk).await {
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#[hdl(sim)]
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let MemoryOperationStart::<_> {
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kind,
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addr,
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write_data,
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rw_mask,
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op_id,
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config: _,
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} = start;
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let mut error = false;
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let mut read_data = vec![0u8; finish_ty.read_data.len()];
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#[hdl(sim)]
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match &kind {
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MemoryOperationKind::Read => {
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for (i, v) in read_data.iter_mut().enumerate() {
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if *rw_mask[i] {
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let addr = addr.as_int().wrapping_add(i as u64);
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let offset =
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addr.wrapping_sub(config.get().address_range.start().0);
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if !config.get().address_range.contains(addr) {
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error = true;
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break;
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}
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*v = contents.as_bytes()[offset as usize];
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println!(
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"reading byte at {addr:#x} (offset={offset:#x}) -> {v:#x} (contents={contents:?})",
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);
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}
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}
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if !error {
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println!(
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"read chunk at {addr:#x}: {:#x?}",
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std::fmt::from_fn(|f| f
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.debug_map()
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.entries(
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read_data
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.iter()
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.enumerate()
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.filter_map(|(i, &v)| rw_mask[i].then(|| (i, v)))
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)
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.finish()),
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addr = addr.as_int(),
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);
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}
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}
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MemoryOperationKind::Write => {
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todo!("write {write_data:?}");
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}
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}
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let finish_kind = if error {
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read_data.fill(0);
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#[hdl(sim)]
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MemoryOperationFinishKind.Error(
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#[hdl(sim)]
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MemoryOperationErrorKind.Generic(),
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)
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} else {
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#[hdl(sim)]
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MemoryOperationFinishKind.Success(kind)
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};
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ops.push_back(Op {
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cycles_left: get_next_delay(delay_sequence_index),
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op_id,
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finish: #[hdl(sim)]
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MemoryOperationFinish::<_> {
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kind: finish_kind,
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read_data,
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config,
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},
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});
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}
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}
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}
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}
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m.extern_module_simulation_fn(
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(cd, input_interface, config, contents),
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async |(cd, input_interface, config, contents), mut sim| {
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// intentionally have a different sequence each time we're reset
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let delay_sequence_index = Cell::new(0);
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sim.resettable(
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cd,
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async |mut sim| {
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sim.write(
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input_interface.next_op_ids,
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#[hdl(sim)]
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(input_interface.ty().next_op_ids).HdlNone(),
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)
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.await;
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sim.write_bool(input_interface.start.ready, false).await;
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sim.write(
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input_interface.finish.data,
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#[hdl(sim)]
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(input_interface.ty().finish.data).HdlNone(),
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)
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.await;
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},
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|sim, ()| {
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run(
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cd,
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input_interface,
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config,
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contents,
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&delay_sequence_index,
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sim,
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)
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},
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)
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.await
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},
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);
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
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struct Memory {
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contents: Interned<str>,
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config: PhantomConst<MemoryInterfaceConfig>,
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}
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impl Memory {
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fn new(
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contents: impl AsRef<str>,
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log2_bus_width_in_bytes: u8,
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address_range: AddressRange,
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) -> Self {
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Self {
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contents: contents.as_ref().intern(),
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config: PhantomConst::new_sized(MemoryInterfaceConfig::new(
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log2_bus_width_in_bytes,
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8,
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FETCH_BLOCK_ID_WIDTH,
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address_range,
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)),
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}
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}
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}
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#[hdl_module(extern)]
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fn mock_cpu(memories: Interned<[Memory]>) {
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const LOG2_BUS_WIDTH: u8 = 3;
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const BUS_WIDTH: usize = 1 << LOG2_BUS_WIDTH;
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let config = PhantomConst::new_sized(MemoryInterfaceConfig::new(
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LOG2_BUS_WIDTH,
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8,
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FETCH_BLOCK_ID_WIDTH,
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AddressRange::Full,
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));
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let output_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
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m.output(MemoryInterface[config]);
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#[hdl]
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let finished: Bool = m.output();
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m.register_clock_for_past(cd.clk);
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#[derive(PartialEq)]
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struct Op {
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addr: u64,
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read_mask: [bool; BUS_WIDTH],
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}
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impl fmt::Debug for Op {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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let Self { addr, read_mask } = self;
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f.debug_struct("Op")
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.field("addr", &fmt::from_fn(|f| write!(f, "{addr:#x}")))
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.field("read_mask", read_mask)
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.finish()
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}
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}
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#[hdl]
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async fn generator(
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cd: Expr<ClockDomain>,
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output_interface: Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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config: PhantomConst<MemoryInterfaceConfig>,
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sequence: &[Op],
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delay_sequence_index: &Cell<u64>,
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mut sim: ExternModuleSimulationState,
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) {
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println!("generator: start");
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let start_ty = MemoryOperationStart[config];
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for (op_index, op) in sequence.iter().enumerate() {
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sim.write(
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output_interface.start.data,
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#[hdl(sim)]
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(output_interface.ty().start.data).HdlNone(),
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)
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.await;
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let delay = get_next_delay(delay_sequence_index);
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println!("generator: delay by {delay}");
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for i in 0..delay {
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println!("generator: delay cycle {i}");
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sim.wait_for_clock_edge(cd.clk).await;
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}
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sim.write(
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output_interface.start.data,
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#[hdl(sim)]
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(output_interface.ty().start.data).HdlSome(
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#[hdl(sim)]
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MemoryOperationStart::<_> {
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kind: #[hdl(sim)]
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MemoryOperationKind.Read(),
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addr: op.addr,
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write_data: &[0u8; BUS_WIDTH][..],
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rw_mask: &op.read_mask[..],
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op_id: op_index.cast_to(start_ty.op_id),
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config,
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},
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),
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)
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.await;
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sim.wait_for_clock_edge(cd.clk).await;
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while !sim
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.read_past_bool(output_interface.start.ready, cd.clk)
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.await
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{
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sim.wait_for_clock_edge(cd.clk).await;
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}
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}
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}
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#[hdl]
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async fn checker(
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cd: Expr<ClockDomain>,
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output_interface: Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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config: PhantomConst<MemoryInterfaceConfig>,
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sequence: &[Op],
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memories: Interned<[Memory]>,
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delay_sequence_index: &Cell<u64>,
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sim: &mut ExternModuleSimulationState,
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) {
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println!("checker: start");
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for op in sequence {
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sim.write_bool(output_interface.finish.ready, false).await;
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let delay = get_next_delay(delay_sequence_index);
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println!("checker: delay {delay}");
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for _ in 0..delay {
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sim.wait_for_clock_edge(cd.clk).await;
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}
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sim.write_bool(output_interface.finish.ready, true).await;
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sim.wait_for_clock_edge(cd.clk).await;
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let mut finish = loop {
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#[hdl(sim)]
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if let HdlSome(finish) = sim.read_past(output_interface.finish.data, cd.clk).await {
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break finish;
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}
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sim.wait_for_clock_edge(cd.clk).await;
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};
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let finish_unmasked = finish.clone();
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for (v, &mask) in finish.read_data.iter_mut().zip(&op.read_mask) {
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if !mask {
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*v = 0u8.to_sim_value(); // ignore outputs for ignored bytes
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}
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}
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let mut expected_finish = memories
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.iter()
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.find(|m| m.config.get().address_range.contains(op.addr))
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.and_then(
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|&Memory {
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config: memory_config,
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contents,
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}|
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-> Option<_> {
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let mut read_data = [0u8; BUS_WIDTH];
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let mut first_enabled = None;
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let mut last_enabled = None;
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for (i, &mask) in op.read_mask.iter().enumerate() {
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if mask {
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first_enabled.get_or_insert(i);
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last_enabled = Some(i);
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read_data[i] = *contents.as_bytes().get(
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usize::try_from(
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op.addr.wrapping_add(i as u64).wrapping_sub(
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memory_config.get().address_range.start().0,
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),
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)
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.ok()?,
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)?;
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}
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}
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if let (Some(first_enabled), Some(last_enabled)) =
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(first_enabled, last_enabled)
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{
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let log2_bus_width_in_bytes =
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memory_config.get().log2_bus_width_in_bytes;
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if first_enabled >> log2_bus_width_in_bytes
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!= last_enabled >> log2_bus_width_in_bytes
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{
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// this operation requires more than one operation at the final memory,
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// so it gets turned into an error since we're using
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// memory_interface_adapter_no_split
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return None;
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}
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}
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Some(
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#[hdl(sim)]
|
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MemoryOperationFinish::<_> {
|
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kind: #[hdl(sim)]
|
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MemoryOperationFinishKind.Success(
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#[hdl(sim)]
|
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MemoryOperationKind.Read(),
|
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),
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read_data: &read_data[..],
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config,
|
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},
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)
|
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},
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)
|
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.unwrap_or_else(|| {
|
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#[hdl(sim)]
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MemoryOperationFinish::<_> {
|
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kind: #[hdl(sim)]
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MemoryOperationFinishKind.Error(
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#[hdl(sim)]
|
||||
MemoryOperationErrorKind.Generic(),
|
||||
),
|
||||
read_data: &[0u8; BUS_WIDTH][..],
|
||||
config,
|
||||
}
|
||||
});
|
||||
// make SimValue fill in the enum padding so they format the same
|
||||
SimValue::bits_mut(&mut finish);
|
||||
SimValue::bits_mut(&mut expected_finish);
|
||||
assert!(
|
||||
format!("{finish:#?}") == format!("{expected_finish:#?}"),
|
||||
"op={op:#?}\nexpected_finish={expected_finish:#?}\n\
|
||||
finish={finish:#?}\nfinish_unmasked={finish_unmasked:#?}"
|
||||
);
|
||||
}
|
||||
}
|
||||
m.extern_module_simulation_fn(
|
||||
(cd, output_interface, finished, config, memories),
|
||||
async |(cd, output_interface, finished, config, memories), mut sim| {
|
||||
sim.write_bool(finished, false).await;
|
||||
sim.write_bool(output_interface.finish.ready, false).await;
|
||||
sim.write(
|
||||
output_interface.start.data,
|
||||
#[hdl(sim)]
|
||||
(output_interface.ty().start.data).HdlNone(),
|
||||
)
|
||||
.await;
|
||||
|
||||
// intentionally have a different sequence each time we're reset
|
||||
let generator_delay_sequence_index = Cell::new(1 << 63);
|
||||
let checker_delay_sequence_index = Cell::new(1 << 62);
|
||||
let mut sequence = Vec::new();
|
||||
sequence.push(Op {
|
||||
addr: !0 << 16,
|
||||
read_mask: [true; _],
|
||||
});
|
||||
for (i, memory) in memories.iter().enumerate() {
|
||||
assert!(
|
||||
memory
|
||||
.config
|
||||
.get()
|
||||
.address_range
|
||||
.start()
|
||||
.0
|
||||
.is_multiple_of(BUS_WIDTH as u64)
|
||||
);
|
||||
assert!(
|
||||
memory
|
||||
.config
|
||||
.get()
|
||||
.address_range
|
||||
.last()
|
||||
.wrapping_add(1)
|
||||
.is_multiple_of(BUS_WIDTH as u64)
|
||||
);
|
||||
if i == 0 {
|
||||
for log2_read_size in 0..=LOG2_BUS_WIDTH {
|
||||
let read_size = 1 << log2_read_size;
|
||||
for offset in (0..BUS_WIDTH).step_by(read_size) {
|
||||
sequence.push(Op {
|
||||
addr: memory.config.get().address_range.start().0,
|
||||
read_mask: std::array::from_fn(|byte_index| {
|
||||
byte_index
|
||||
.checked_sub(offset)
|
||||
.is_some_and(|v| v < read_size)
|
||||
}),
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
for (addr, chunk) in (memory.config.get().address_range.start().0..)
|
||||
.step_by(BUS_WIDTH)
|
||||
.zip(memory.contents.as_bytes().chunks(BUS_WIDTH))
|
||||
{
|
||||
let mut op = Op {
|
||||
addr,
|
||||
read_mask: [true; BUS_WIDTH],
|
||||
};
|
||||
op.read_mask[chunk.len()..].fill(false);
|
||||
if sequence.last() != Some(&op) {
|
||||
sequence.push(op);
|
||||
}
|
||||
}
|
||||
}
|
||||
sim.fork_join_scope(async |scope, mut sim| {
|
||||
scope.spawn_detached(async |_scope, mut sim| {
|
||||
sim.resettable(
|
||||
cd,
|
||||
async |mut sim| {
|
||||
sim.write(
|
||||
output_interface.start.data,
|
||||
#[hdl(sim)]
|
||||
(output_interface.ty().start.data).HdlNone(),
|
||||
)
|
||||
.await;
|
||||
},
|
||||
|sim, ()| {
|
||||
generator(
|
||||
cd,
|
||||
output_interface,
|
||||
config,
|
||||
&sequence,
|
||||
&generator_delay_sequence_index,
|
||||
sim,
|
||||
)
|
||||
},
|
||||
)
|
||||
.await
|
||||
});
|
||||
sim.resettable(
|
||||
cd,
|
||||
async |mut sim| {
|
||||
sim.write_bool(finished, false).await;
|
||||
sim.write_bool(output_interface.finish.ready, false).await;
|
||||
},
|
||||
async |mut sim, ()| {
|
||||
checker(
|
||||
cd,
|
||||
output_interface,
|
||||
config,
|
||||
&sequence,
|
||||
memories,
|
||||
&checker_delay_sequence_index,
|
||||
&mut sim,
|
||||
)
|
||||
.await;
|
||||
sim.write_bool(finished, true).await;
|
||||
loop {
|
||||
sim.write_bool(output_interface.finish.ready, true).await;
|
||||
sim.wait_for_clock_edge(cd.clk).await;
|
||||
#[hdl(sim)]
|
||||
if let HdlSome(finish) =
|
||||
sim.read_past(output_interface.finish.data, cd.clk).await
|
||||
{
|
||||
panic!("spurious finished transaction: {finish:#?}");
|
||||
}
|
||||
}
|
||||
},
|
||||
)
|
||||
.await
|
||||
})
|
||||
.await;
|
||||
},
|
||||
);
|
||||
}
|
||||
|
||||
#[hdl_module]
|
||||
fn memory_interface_adapter_no_split_dut(memories: Interned<[Memory]>) {
|
||||
#[hdl]
|
||||
let cd: ClockDomain = m.input();
|
||||
#[hdl]
|
||||
let finished: Bool = m.output();
|
||||
#[hdl]
|
||||
let mock_cpu = instance(mock_cpu(memories));
|
||||
connect(mock_cpu.cd, cd);
|
||||
connect(finished, mock_cpu.finished);
|
||||
let (fields, inputs): (Vec<_>, Vec<_>) = memories
|
||||
.iter()
|
||||
.enumerate()
|
||||
.map(|(index, &memory)| {
|
||||
let mock_mem = instance_with_loc(
|
||||
&format!("mock_mem_{index}"),
|
||||
mock_memory(memory),
|
||||
SourceLocation::caller(),
|
||||
);
|
||||
connect(mock_mem.cd, cd);
|
||||
(
|
||||
BundleField {
|
||||
name: format!("{index}").intern_deref(),
|
||||
flipped: false,
|
||||
ty: MemoryInterface[memory.config].canonical(),
|
||||
},
|
||||
mock_mem.input_interface,
|
||||
)
|
||||
})
|
||||
.unzip();
|
||||
let bundle_ty = Bundle::new(fields.intern_deref());
|
||||
#[hdl]
|
||||
let adapter = instance(memory_interface_adapter_no_split(
|
||||
mock_cpu.ty().output_interface.config,
|
||||
bundle_ty,
|
||||
));
|
||||
connect(adapter.cd, cd);
|
||||
connect(adapter.input_interface, mock_cpu.output_interface);
|
||||
for (field, input) in bundle_ty.fields().into_iter().zip(inputs) {
|
||||
connect(input, Expr::field(adapter.output_interfaces, &field.name));
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[hdl]
|
||||
fn test_memory_interface_adapter_no_split() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let memories = vec![
|
||||
Memory::new("Testing", 3, AddressRange::from_range(0x1000..0x2000)),
|
||||
Memory::new("Memory2.", 2, AddressRange::from_range(0x2000..0x2010)),
|
||||
Memory::new("Contents Test", 0, AddressRange::from_range(0x3000..0x3100)),
|
||||
]
|
||||
.intern_deref();
|
||||
let m = memory_interface_adapter_no_split_dut(memories);
|
||||
let mut sim = Simulation::new(m);
|
||||
let writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
struct DumpVcdOnDrop {
|
||||
writer: Option<RcWriter>,
|
||||
}
|
||||
impl Drop for DumpVcdOnDrop {
|
||||
fn drop(&mut self) {
|
||||
if let Some(mut writer) = self.writer.take() {
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
}
|
||||
}
|
||||
}
|
||||
let mut writer = DumpVcdOnDrop {
|
||||
writer: Some(writer),
|
||||
};
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
for _cycle in 0..1000 {
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
}
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
assert!(sim.read_bool(sim.io().finished));
|
||||
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/memory_interface_adapter_no_split.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
@ -6,8 +6,8 @@ use cpu::{
|
|||
MemoryInterface, MemoryInterfaceConfig, MemoryOperationErrorKind, MemoryOperationFinish,
|
||||
MemoryOperationFinishKind, MemoryOperationKind, MemoryOperationStart,
|
||||
simple_uart::{
|
||||
ReceiverQueueStatus, SIMPLE_UART_RECEIVE_OFFSET, SIMPLE_UART_SIZE,
|
||||
SIMPLE_UART_STATUS_OFFSET, SIMPLE_UART_TRANSMIT_OFFSET, receiver, receiver_no_queue,
|
||||
ReceiverQueueStatus, SIMPLE_UART_RECEIVE_OFFSET, SIMPLE_UART_STATUS_OFFSET,
|
||||
SIMPLE_UART_TRANSMIT_OFFSET, SIMPLE_UART_USED_SIZE, receiver, receiver_no_queue,
|
||||
simple_uart, simple_uart_memory_interface_config, transmitter, uart_clock_gen,
|
||||
},
|
||||
},
|
||||
|
|
@ -920,10 +920,10 @@ fn test_simple_uart() {
|
|||
|
||||
for i in 0..2 * BUS_WIDTH_IN_BYTES as u64 {
|
||||
mem_op_runner
|
||||
.read_bytes::<1>(SIMPLE_UART_SIZE.get() + i, 1)
|
||||
.read_bytes::<1>(SIMPLE_UART_USED_SIZE.get() + i, 1)
|
||||
.unwrap_err();
|
||||
mem_op_runner
|
||||
.write_bytes(SIMPLE_UART_SIZE.get() + i, [0], 1)
|
||||
.write_bytes(SIMPLE_UART_USED_SIZE.get() + i, [0], 1)
|
||||
.unwrap_err();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue