forked from libre-chip/cpu
start debugging reg_alloc with simulator
This commit is contained in:
parent
bf34dee043
commit
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SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 1211 additions and 37 deletions
880
crates/cpu/tests/expected/reg_alloc.vcd
Normal file
880
crates/cpu/tests/expected/reg_alloc.vcd
Normal file
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@ -0,0 +1,880 @@
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$var reg 1 r" \[4] $end
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$var reg 1 s" \[5] $end
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$upscope $end
|
||||
$var wire 1 4# reduced_count_0_8 $end
|
||||
$var wire 1 5# reduced_count_overflowed_0_8 $end
|
||||
$scope struct reduced_alloc_nums_0_8 $end
|
||||
$var wire 3 6# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 7# reduced_count_8_10 $end
|
||||
$var wire 1 8# reduced_count_overflowed_8_10 $end
|
||||
$scope struct reduced_alloc_nums_8_10 $end
|
||||
$var wire 1 9# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 :# reduced_count_10_12 $end
|
||||
$var wire 1 ;# reduced_count_overflowed_10_12 $end
|
||||
$scope struct reduced_alloc_nums_10_12 $end
|
||||
$var wire 1 <# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 =# reduced_count_8_12 $end
|
||||
$var wire 1 ># reduced_count_overflowed_8_12 $end
|
||||
$scope struct reduced_alloc_nums_8_12 $end
|
||||
$var wire 2 ?# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 @# reduced_count_12_14 $end
|
||||
$var wire 1 A# reduced_count_overflowed_12_14 $end
|
||||
$scope struct reduced_alloc_nums_12_14 $end
|
||||
$var wire 1 B# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 C# reduced_count_14_16 $end
|
||||
$var wire 1 D# reduced_count_overflowed_14_16 $end
|
||||
$scope struct reduced_alloc_nums_14_16 $end
|
||||
$var wire 1 E# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 F# reduced_count_12_16 $end
|
||||
$var wire 1 G# reduced_count_overflowed_12_16 $end
|
||||
$scope struct reduced_alloc_nums_12_16 $end
|
||||
$var wire 2 H# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 I# reduced_count_8_16 $end
|
||||
$var wire 1 J# reduced_count_overflowed_8_16 $end
|
||||
$scope struct reduced_alloc_nums_8_16 $end
|
||||
$var wire 3 K# \[0] $end
|
||||
$upscope $end
|
||||
$var wire 1 L# reduced_count_0_16 $end
|
||||
$var wire 1 M# reduced_count_overflowed_0_16 $end
|
||||
$scope struct reduced_alloc_nums_0_16 $end
|
||||
$var wire 4 N# \[0] $end
|
||||
$upscope $end
|
||||
$scope struct firing_data $end
|
||||
$var string 1 O# \$tag $end
|
||||
$var wire 4 P# HdlSome $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$dumpvars
|
||||
0!
|
||||
1"
|
||||
sHdlSome\x20(1) #
|
||||
sAluBranch\x20(0) $
|
||||
sAddSub\x20(0) %
|
||||
s0 &
|
||||
b1 '
|
||||
b10 (
|
||||
b11 )
|
||||
b100 *
|
||||
b1001000110100 +
|
||||
0,
|
||||
sFull64\x20(0) -
|
||||
1.
|
||||
1/
|
||||
10
|
||||
11
|
||||
s0 2
|
||||
b1 3
|
||||
b10 4
|
||||
b11 5
|
||||
b100 6
|
||||
b1001000110100 7
|
||||
08
|
||||
sFull64\x20(0) 9
|
||||
1:
|
||||
1;
|
||||
1<
|
||||
1=
|
||||
s0 >
|
||||
b1 ?
|
||||
b10 @
|
||||
b11 A
|
||||
b100 B
|
||||
b1001000110100 C
|
||||
0D
|
||||
sFull64\x20(0) E
|
||||
b1111 F
|
||||
sReadL2Reg\x20(0) G
|
||||
0H
|
||||
b1 I
|
||||
b10 J
|
||||
b11 K
|
||||
b100 L
|
||||
b1001000110100 M
|
||||
0N
|
||||
0O
|
||||
b1 P
|
||||
b10 Q
|
||||
b11 R
|
||||
b100 S
|
||||
b1001000110100 T
|
||||
0U
|
||||
sLoad\x20(0) V
|
||||
0W
|
||||
b1 X
|
||||
b10 Y
|
||||
b11 Z
|
||||
b100 [
|
||||
b1001000110100 \
|
||||
0]
|
||||
0^
|
||||
b1 _
|
||||
b10 `
|
||||
b11 a
|
||||
b100 b
|
||||
b1001000110100 c
|
||||
0d
|
||||
1e
|
||||
b1000000000000 f
|
||||
1g
|
||||
sHdlSome\x20(1) h
|
||||
sAluBranch\x20(0) i
|
||||
sLogical\x20(2) j
|
||||
s0 k
|
||||
b10 l
|
||||
b11 m
|
||||
b100 n
|
||||
b0 o
|
||||
b0 p
|
||||
0q
|
||||
sFull64\x20(0) r
|
||||
0s
|
||||
1t
|
||||
1u
|
||||
0v
|
||||
s0 w
|
||||
b10 x
|
||||
b11 y
|
||||
b100 z
|
||||
b0 {
|
||||
b0 |
|
||||
0}
|
||||
sFull64\x20(0) ~
|
||||
0!"
|
||||
1""
|
||||
1#"
|
||||
0$"
|
||||
s0 %"
|
||||
b10 &"
|
||||
b11 '"
|
||||
b100 ("
|
||||
b0 )"
|
||||
b0 *"
|
||||
0+"
|
||||
sFull64\x20(0) ,"
|
||||
b110 -"
|
||||
sReadL2Reg\x20(0) ."
|
||||
1/"
|
||||
b10 0"
|
||||
b11 1"
|
||||
b100 2"
|
||||
b0 3"
|
||||
b0 4"
|
||||
05"
|
||||
16"
|
||||
b10 7"
|
||||
b11 8"
|
||||
b100 9"
|
||||
b0 :"
|
||||
b0 ;"
|
||||
0<"
|
||||
sLoad\x20(0) ="
|
||||
1>"
|
||||
b10 ?"
|
||||
b11 @"
|
||||
b100 A"
|
||||
b0 B"
|
||||
b0 C"
|
||||
0D"
|
||||
1E"
|
||||
b10 F"
|
||||
b11 G"
|
||||
b100 H"
|
||||
b0 I"
|
||||
b0 J"
|
||||
0K"
|
||||
0L"
|
||||
b1000000000100 M"
|
||||
1N"
|
||||
sHdlNone\x20(0) O"
|
||||
sTrap\x20(0) P"
|
||||
1Q"
|
||||
1R"
|
||||
1S"
|
||||
sHdlSome\x20(1) T"
|
||||
0U"
|
||||
sHdlSome\x20(1) V"
|
||||
0W"
|
||||
sAluBranch\x20(0) X"
|
||||
1Y"
|
||||
sHdlSome\x20(1) Z"
|
||||
0["
|
||||
0\"
|
||||
sAluBranch\x20(0) ]"
|
||||
1^"
|
||||
sHdlSome\x20(1) _"
|
||||
0`"
|
||||
0a"
|
||||
0b"
|
||||
1c"
|
||||
0d"
|
||||
1e"
|
||||
0f"
|
||||
1g"
|
||||
sHdlNone\x20(0) h"
|
||||
b0 i"
|
||||
1j"
|
||||
sHdlSome\x20(1) k"
|
||||
b0 l"
|
||||
0m"
|
||||
0n"
|
||||
0o"
|
||||
0p"
|
||||
0q"
|
||||
0r"
|
||||
0s"
|
||||
0t"
|
||||
0u"
|
||||
0v"
|
||||
0w"
|
||||
0x"
|
||||
0y"
|
||||
0z"
|
||||
0{"
|
||||
0|"
|
||||
0}"
|
||||
sHdlNone\x20(0) ~"
|
||||
b0 !#
|
||||
0"#
|
||||
1##
|
||||
0$#
|
||||
0%#
|
||||
1&#
|
||||
0'#
|
||||
0(#
|
||||
1)#
|
||||
b0 *#
|
||||
0+#
|
||||
1,#
|
||||
0-#
|
||||
0.#
|
||||
1/#
|
||||
00#
|
||||
01#
|
||||
12#
|
||||
b0 3#
|
||||
04#
|
||||
15#
|
||||
b0 6#
|
||||
07#
|
||||
18#
|
||||
09#
|
||||
0:#
|
||||
1;#
|
||||
0<#
|
||||
0=#
|
||||
1>#
|
||||
b0 ?#
|
||||
0@#
|
||||
1A#
|
||||
0B#
|
||||
0C#
|
||||
1D#
|
||||
0E#
|
||||
0F#
|
||||
1G#
|
||||
b0 H#
|
||||
0I#
|
||||
1J#
|
||||
b0 K#
|
||||
0L#
|
||||
1M#
|
||||
b0 N#
|
||||
sHdlNone\x20(0) O#
|
||||
b0 P#
|
||||
0Q#
|
||||
1R#
|
||||
sHdlNone\x20(0) S#
|
||||
b0 T#
|
||||
1U#
|
||||
sHdlSome\x20(1) V#
|
||||
b0 W#
|
||||
0X#
|
||||
$end
|
||||
#500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#1000000
|
||||
0!
|
||||
0"
|
||||
0b"
|
||||
0c"
|
||||
0d"
|
||||
0e"
|
||||
0f"
|
||||
0g"
|
||||
0Q#
|
||||
0R#
|
||||
#1500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#2000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#2500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#3000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#3500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#4000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#4500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#5000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#5500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#6000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#6500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#7000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#7500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#8000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#8500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#9000000
|
||||
0!
|
||||
0b"
|
||||
0d"
|
||||
0f"
|
||||
0Q#
|
||||
#9500000
|
||||
1!
|
||||
1b"
|
||||
1d"
|
||||
1f"
|
||||
1Q#
|
||||
#10000000
|
||||
101
crates/cpu/tests/reg_alloc.rs
Normal file
101
crates/cpu/tests/reg_alloc.rs
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
// See Notices.txt for copyright information
|
||||
|
||||
use cpu::{
|
||||
config::CpuConfig,
|
||||
instruction::{
|
||||
AddSubMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOp, OutputIntegerMode,
|
||||
COMMON_MOP_2_IMM_WIDTH, COMMON_MOP_3_IMM_WIDTH,
|
||||
},
|
||||
reg_alloc::{reg_alloc, FetchedDecodedMOp},
|
||||
unit::UnitKind,
|
||||
};
|
||||
use fayalite::{
|
||||
prelude::*,
|
||||
sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
|
||||
util::RcWriter,
|
||||
};
|
||||
use std::num::NonZeroUsize;
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_reg_alloc() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut config = CpuConfig::new(vec![UnitKind::AluBranch]);
|
||||
config.fetch_width = NonZeroUsize::new(2).unwrap();
|
||||
let mut sim = Simulation::new(reg_alloc(&config));
|
||||
let mut writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
let fetch_decode_interface = sim.io().fetch_decode_interface;
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
sim.write_bool(fetch_decode_interface.fetch_decode_special_op.ready, true);
|
||||
sim.write(
|
||||
fetch_decode_interface.decoded_insns[0].data,
|
||||
HdlSome(
|
||||
#[hdl]
|
||||
FetchedDecodedMOp {
|
||||
uop: MOp.AluBranch(MOp.AluBranch.AddSub(
|
||||
#[hdl]
|
||||
AddSubMOp {
|
||||
alu_common: #[hdl]
|
||||
AluCommonMOp {
|
||||
common: CommonMOp::new(
|
||||
0_hdl_u0,
|
||||
1u8,
|
||||
[2u8, 3u8, 4u8],
|
||||
0x1234.cast_to(SInt[COMMON_MOP_3_IMM_WIDTH]),
|
||||
),
|
||||
output_integer_mode: OutputIntegerMode.Full64(),
|
||||
},
|
||||
invert_src0: true,
|
||||
invert_carry_in: true,
|
||||
invert_carry_out: true,
|
||||
add_pc: true,
|
||||
},
|
||||
)),
|
||||
is_unrelated_pc: true,
|
||||
pc: 0x1000_hdl_u64,
|
||||
},
|
||||
),
|
||||
);
|
||||
sim.write(
|
||||
fetch_decode_interface.decoded_insns[1].data,
|
||||
HdlSome(
|
||||
#[hdl]
|
||||
FetchedDecodedMOp {
|
||||
uop: MOp.AluBranch(MOp.AluBranch.Logical(
|
||||
#[hdl]
|
||||
LogicalMOp {
|
||||
alu_common: #[hdl]
|
||||
AluCommonMOp {
|
||||
common: CommonMOp::new(
|
||||
0_hdl_u0,
|
||||
2u8,
|
||||
[3u8, 4u8],
|
||||
SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
|
||||
),
|
||||
output_integer_mode: OutputIntegerMode.Full64(),
|
||||
},
|
||||
lut: 0b0110_hdl_u4,
|
||||
},
|
||||
)),
|
||||
is_unrelated_pc: false,
|
||||
pc: 0x1004_hdl_u64,
|
||||
},
|
||||
),
|
||||
);
|
||||
for cycle in 0..10 {
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
}
|
||||
// FIXME: vcd is just whatever reg_alloc does now, which isn't known to be correct
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/reg_alloc.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue