forked from libre-chip/cpu
WIP adding next_pc: add call stack
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parent
7a77c02cda
commit
033d5d4f34
SSH key fingerprint:
SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 136 additions and 49 deletions
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@ -17,7 +17,6 @@ use fayalite::{
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int::{UIntInRange, UIntInRangeInclusive, UIntInRangeType},
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prelude::*,
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sim::value::SimOnlyValueTrait,
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ty::StaticType,
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util::ready_valid::ReadyValid,
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};
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@ -77,11 +76,9 @@ pub enum WipDecodedInsnKind {
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Branch(UInt<64>),
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BranchCond(UInt<64>),
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IndirectBranch,
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IndirectBranchCond,
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Call(UInt<64>),
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CallCond(UInt<64>),
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IndirectCall,
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IndirectCallCond,
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Ret,
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RetCond,
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/// not actually an instruction read from memory, covers stuff like external interrupts, page faults, memory errors, and so on.
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@ -98,11 +95,9 @@ impl WipDecodedInsnKind {
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| Self::Branch(_)
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| Self::BranchCond(_)
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| Self::IndirectBranch
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| Self::IndirectBranchCond
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| Self::Call(_)
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| Self::CallCond(_)
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| Self::IndirectCall
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| Self::IndirectCallCond
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| Self::Ret
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| Self::RetCond
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| Self::Unknown => None,
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@ -267,10 +262,33 @@ impl<T: SimValueDefault, Len: Size> ResetSteps for ArrayType<T, Len> {
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struct CallStack {
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return_addresses: Array<UInt<64>, { CallStack::SIZE }>,
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len: UIntInRangeInclusive<0, { CallStack::SIZE }>,
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top: UIntInRange<0, { CallStack::SIZE }>,
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}
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impl CallStack {
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const SIZE: usize = 16;
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fn push(this: &mut SimValue<CallStack>, value: impl ToSimValue<Type = UInt<64>>) {
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let new_len = *this.len + 1;
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*this.len = if new_len > Self::SIZE {
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Self::SIZE
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} else {
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new_len
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};
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let top = *this.top;
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this.return_addresses[top] = value.into_sim_value();
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*this.top = (top + 1) % Self::SIZE;
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}
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fn pop(this: &mut SimValue<CallStack>) -> Option<u64> {
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if *this.len == 0 {
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None
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} else {
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*this.len -= 1;
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let top = *this.top;
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let top = (top + Self::SIZE - 1) % Self::SIZE;
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*this.top = top;
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Some(this.return_addresses[top].as_int())
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}
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}
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}
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impl SimValueDefault for CallStack {
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@ -281,6 +299,7 @@ impl SimValueDefault for CallStack {
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// something other than zero so you can see the values getting reset
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return_addresses: [!0u64; Self::SIZE],
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len: 0usize.to_sim_value_with_type(self.len),
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top: 0usize.to_sim_value_with_type(self.top),
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}
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}
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}
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@ -292,10 +311,12 @@ impl ResetSteps for CallStack {
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let CallStack {
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return_addresses,
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len,
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top,
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} = this;
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// return_addresses is implemented as a shift register, so it can be all reset at once
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return_addresses.fill(0u64.to_sim_value());
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**len = 0;
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**top = 0;
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ResetStatus::Done
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}
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}
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@ -315,15 +336,13 @@ impl BTBEntryInsnKind {
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WipDecodedInsnKind::NonBranch => None,
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WipDecodedInsnKind::Branch(_)
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| WipDecodedInsnKind::BranchCond(_)
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| WipDecodedInsnKind::IndirectBranch
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| WipDecodedInsnKind::IndirectBranchCond => Some(
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| WipDecodedInsnKind::IndirectBranch => Some(
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#[hdl(sim)]
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BTBEntryInsnKind::Branch(),
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),
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WipDecodedInsnKind::Call(_)
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| WipDecodedInsnKind::CallCond(_)
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| WipDecodedInsnKind::IndirectCall
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| WipDecodedInsnKind::IndirectCallCond => Some(
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| WipDecodedInsnKind::IndirectCall => Some(
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#[hdl(sim)]
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BTBEntryInsnKind::Call(),
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),
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@ -385,11 +404,6 @@ impl BTBEntryAddrKind {
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#[hdl(sim)]
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Self::Indirect(),
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),
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WipDecodedInsnKind::IndirectBranchCond | WipDecodedInsnKind::IndirectCallCond => Some(
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// our conditional branch prediction doesn't work with indirect branches
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#[hdl(sim)]
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Self::Indirect(),
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),
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WipDecodedInsnKind::Interrupt(_) => None,
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WipDecodedInsnKind::Unknown => None,
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}
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@ -404,6 +418,8 @@ struct BTBEntry {
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/// when branch is not taken, the next pc to fetch from is `start_pc + fallthrough_offset`.
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/// needed because there may be more than one branch in a fetch block
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fallthrough_offset: UInt<8>,
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/// when a call is made, the return address is `start_pc + after_call_offset`
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after_call_offset: UInt<8>,
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insn_kind: BTBEntryInsnKind,
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addr_kind: BTBEntryAddrKind,
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}
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@ -419,13 +435,48 @@ impl BTBEntry {
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}
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}
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#[hdl]
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struct LFSR31 {
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// MSB is always zero, 32 bits makes it easier to manipulate
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state: UInt<32>,
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}
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impl SimValueDefault for LFSR31 {
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#[hdl]
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fn sim_value_default(self) -> SimValue<Self> {
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#[hdl(sim)]
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Self { state: 1u32 }
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}
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}
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impl LFSR31 {
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fn next(this: &mut SimValue<Self>) -> u32 {
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let state = this.state.as_int();
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let state = if state == 0 {
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1u32
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} else {
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// a maximal-length 31-bit LFSR
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let lsb = ((state >> 30) ^ (state >> 27)) & 1;
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let msb = (state << 1) & ((1 << 31) - 1);
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lsb | msb
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};
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*this.state = state.into();
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state
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}
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}
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#[hdl]
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struct BranchTargetBuffer {
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branch_pc_to_target_map: Array<HdlOption<BTBEntry>, { BranchTargetBuffer::SIZE }>,
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next_index_to_replace_lfsr: LFSR31,
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}
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impl BranchTargetBuffer {
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const SIZE: usize = 16;
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const LOG2_SIZE: usize = 4;
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const SIZE: usize = 1 << Self::LOG2_SIZE;
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fn next_index_to_replace(this: &mut SimValue<Self>) -> usize {
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LFSR31::next(&mut this.next_index_to_replace_lfsr) as usize % Self::SIZE
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}
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}
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impl SimValueDefault for BranchTargetBuffer {
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@ -440,10 +491,12 @@ impl SimValueDefault for BranchTargetBuffer {
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start_pc: !0u64,
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target_pc: !0u64,
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fallthrough_offset: !0u8,
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after_call_offset: !0u8,
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insn_kind: BTBEntryInsnKind.Call(),
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addr_kind: BTBEntryAddrKind.CondNotTaken(),
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},
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); Self::SIZE],
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next_index_to_replace_lfsr: LFSR31.sim_value_default(),
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}
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}
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}
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@ -454,7 +507,9 @@ impl ResetSteps for BranchTargetBuffer {
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#[hdl(sim)]
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let BranchTargetBuffer {
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branch_pc_to_target_map,
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next_index_to_replace_lfsr,
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} = this;
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*next_index_to_replace_lfsr = LFSR31.sim_value_default();
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ResetSteps::reset_step(branch_pc_to_target_map, step)
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}
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}
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@ -850,11 +905,11 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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fetch_block_id: expected_fetch_block_id,
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btb_entry,
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btb_entry_index,
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next_pc,
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next_pc: orig_next_pc,
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} = fetch_queue_entry;
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let insns = ArrayVec::elements_sim_ref(&insns);
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if let Some(target_pc) = WipDecodedInsnKind::interrupt_target_pc_sim(&insns[0].kind) {
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if **target_pc != *next_pc {
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if *target_pc != orig_next_pc {
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*this.cancel_in_progress_fetches = true;
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this.pc = target_pc.clone();
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}
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@ -862,6 +917,7 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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}
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let start_pc = insns[0].pc.as_int();
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let mut fallthrough_offset = 0u8;
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let mut after_call_offset = 0u8;
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let mut btb_entry_fields = None;
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let mut eval_cond_branch = || -> SimValue<BTBEntryAddrKind> {
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todo!();
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@ -889,13 +945,13 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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BTBEntryInsnKind::Branch();
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addr_kind = #[hdl(sim)]
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BTBEntryAddrKind::Unconditional();
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Some(target_pc.clone())
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Some(target_pc.as_int())
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}
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WipDecodedInsnKind::BranchCond(target_pc) => {
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Branch();
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addr_kind = eval_cond_branch();
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Some(target_pc.clone())
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Some(target_pc.as_int())
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}
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WipDecodedInsnKind::IndirectBranch => {
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insn_kind = #[hdl(sim)]
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@ -904,26 +960,18 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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BTBEntryAddrKind::Indirect();
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None
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}
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WipDecodedInsnKind::IndirectBranchCond => {
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// our conditional branch prediction doesn't work with indirect branches
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Branch();
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addr_kind = #[hdl(sim)]
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BTBEntryAddrKind::Indirect();
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None
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}
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WipDecodedInsnKind::Call(target_pc) => {
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Call();
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addr_kind = #[hdl(sim)]
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BTBEntryAddrKind::Unconditional();
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Some(target_pc.clone())
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Some(target_pc.as_int())
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}
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WipDecodedInsnKind::CallCond(target_pc) => {
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Call();
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addr_kind = eval_cond_branch();
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Some(target_pc.clone())
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Some(target_pc.as_int())
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}
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WipDecodedInsnKind::IndirectCall => {
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insn_kind = #[hdl(sim)]
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@ -932,14 +980,6 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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BTBEntryAddrKind::Indirect();
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None
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}
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WipDecodedInsnKind::IndirectCallCond => {
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// our conditional branch prediction doesn't work with indirect calls
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Call();
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addr_kind = #[hdl(sim)]
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BTBEntryAddrKind::Indirect();
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None
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}
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WipDecodedInsnKind::Ret => {
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insn_kind = #[hdl(sim)]
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BTBEntryInsnKind::Ret();
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@ -969,28 +1009,70 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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}
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btb_entry_fields = Some((insn_kind, addr_kind, target_pc));
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fallthrough_offset += size_in_bytes.cast_to_static::<UInt<8>>().as_int();
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#[hdl(sim)]
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match insn_kind {
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BTBEntryInsnKind::Call => after_call_offset = fallthrough_offset,
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BTBEntryInsnKind::Branch | BTBEntryInsnKind::Ret | BTBEntryInsnKind::Unknown => {}
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}
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}
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if let Some((insn_kind, addr_kind, target_pc)) = btb_entry_fields {
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let expected_btb_entry = #[hdl(sim)]
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let new_next_pc = if let Some((insn_kind, addr_kind, mut target_pc)) = btb_entry_fields {
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// add/update BTBEntry if it doesn't match
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let btb_entry_index = #[hdl(sim)]
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if let HdlSome(btb_entry) = btb_entry {
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// verify it hasn't been changed meanwhile
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#[hdl(sim)]
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if let HdlSome(entry) =
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&this.branch_target_buffer.branch_pc_to_target_map[*btb_entry_index]
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{
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// we have a btb entry, check if it has been modified
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if entry.start_pc == btb_entry.start_pc {
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// we found the correct BTBEntry
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if target_pc.is_none() {
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// save the existing target_pc if we know it
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target_pc = Some(entry.target_pc.as_int());
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}
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Some(*btb_entry_index)
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} else {
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None
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}
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} else {
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None
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}
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} else {
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None
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};
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let btb_entry_index = btb_entry_index.unwrap_or_else(|| {
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// we need to add a new entry, pick an entry to replace
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BranchTargetBuffer::next_index_to_replace(&mut this.branch_target_buffer)
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});
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let new_next_pc = #[hdl(sim)]
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match insn_kind {
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BTBEntryInsnKind::Branch => {}
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BTBEntryInsnKind::Call => {
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CallStack::push(&mut this.speculative_call_stack, todo!());
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todo!()
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}
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BTBEntryInsnKind::Ret => {
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target_pc = CallStack::pop(&mut this.speculative_call_stack).or(target_pc);
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}
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};
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let new_entry = #[hdl(sim)]
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BTBEntry {
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start_pc,
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target_pc: target_pc.unwrap_or_else(|| 0u64.to_sim_value()),
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target_pc: target_pc.unwrap_or(0u64),
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fallthrough_offset,
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after_call_offset,
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insn_kind,
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addr_kind,
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};
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// add/update BTBEntry if it doesn't match
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#[hdl(sim)]
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if let HdlSome(btb_entry) = btb_entry {
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todo!()
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} else {
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// add BTBEntry
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todo!()
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}
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let entry_mut = &mut this.branch_target_buffer.branch_pc_to_target_map[btb_entry_index];
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*entry_mut = #[hdl(sim)]
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HdlSome(new_entry);
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new_next_pc
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} else {
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#[hdl(sim)]
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if let HdlSome(btb_entry) = btb_entry {
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// remove BTBEntry
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// the fetched instructions do not need a BTBEntry, remove the BTBEntry if it still exists
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let entry_mut =
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&mut this.branch_target_buffer.branch_pc_to_target_map[*btb_entry_index];
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// verify it hasn't been changed meanwhile
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@ -1002,6 +1084,11 @@ impl<C: Type + PhantomConstGet<CpuConfig>> NextPcState<C> {
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}
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}
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}
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start_pc + u64::from(fallthrough_offset)
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};
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if new_next_pc != orig_next_pc.as_int() {
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*this.cancel_in_progress_fetches = true;
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*this.pc = new_next_pc.into();
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}
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}
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}
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