forked from libre-chip/cpu
WIP adding memory_interface_adaptor
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 638 additions and 2 deletions
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@ -2,8 +2,18 @@
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// See Notices.txt for copyright information
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use crate::{config::CpuConfig, next_pc::FETCH_BLOCK_ID_WIDTH, util::array_vec::ArrayVec};
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use fayalite::{prelude::*, util::ready_valid::ReadyValid};
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use std::num::{NonZeroU64, NonZeroUsize, Wrapping};
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use fayalite::{
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bundle::BundleType,
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expr::Valueless,
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int::{UIntInRangeInclusiveType, UIntInRangeType},
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intern::{Intern, Interned},
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prelude::*,
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util::ready_valid::{ReadyValid, queue},
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};
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use std::{
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fmt,
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num::{NonZeroU64, NonZeroUsize, Wrapping},
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};
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pub mod simple_uart;
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@ -180,6 +190,7 @@ pub struct MemoryOperationFinish<C: PhantomConstGet<MemoryInterfaceConfig>> {
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#[hdl(no_static)]
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pub struct MemoryInterface<C: PhantomConstGet<MemoryInterfaceConfig>> {
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pub start: ReadyValid<MemoryOperationStart<C>>,
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/// started operations must finish in the same order they started in
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#[hdl(flip)]
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pub finish: ReadyValid<MemoryOperationFinish<C>>,
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/// for debugging
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@ -187,3 +198,628 @@ pub struct MemoryInterface<C: PhantomConstGet<MemoryInterfaceConfig>> {
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pub next_op_ids: HdlOption<ArrayVec<MemoryInterfaceOpId<C>, MemoryInterfaceQueueCapacity<C>>>,
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pub config: C,
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}
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pub const fn memory_interface_always_error_config(
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base_config: MemoryInterfaceConfig,
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) -> MemoryInterfaceConfig {
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let MemoryInterfaceConfig {
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log2_bus_width_in_bytes,
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queue_capacity: _,
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op_id_width,
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address_range: _,
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} = base_config;
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MemoryInterfaceConfig {
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log2_bus_width_in_bytes,
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queue_capacity: const { NonZeroUsize::new(1).unwrap() },
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op_id_width,
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address_range: AddressRange::Full,
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}
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}
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#[hdl_module]
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pub fn memory_interface_always_error(config: PhantomConst<MemoryInterfaceConfig>) {
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assert_eq!(
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*config.get(),
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memory_interface_always_error_config(*config.get()),
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);
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#[hdl]
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let input_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
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m.input(MemoryInterface[config]);
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connect(
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input_interface.next_op_ids,
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input_interface.ty().next_op_ids.HdlNone(),
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);
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connect(input_interface.start.ready, input_interface.finish.ready);
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connect(
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input_interface.finish.data,
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input_interface.ty().finish.data.HdlNone(),
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);
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#[hdl]
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if let HdlSome(_) = input_interface.start.data {
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connect(
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input_interface.finish.data,
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HdlSome(
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#[hdl]
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MemoryOperationFinish::<_> {
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kind: MemoryOperationFinishKind.Error(MemoryOperationErrorKind.Generic()),
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read_data: repeat(0u8, MemoryInterfaceBusWidthInBytes[config]),
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config,
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},
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),
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);
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}
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}
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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pub struct MemoryInterfacesBundleFieldPath(pub Interned<[Interned<str>]>);
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impl MemoryInterfacesBundleFieldPath {
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pub fn from_slice(path: &[Interned<str>]) -> Self {
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Self(path.intern())
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}
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}
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impl fmt::Display for MemoryInterfacesBundleFieldPath {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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if self.0.is_empty() {
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return f.write_str("<empty path>");
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}
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for (i, name) in self.0.iter().enumerate() {
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if i != 0 {
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f.write_str(".")?;
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}
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if name.is_empty() || name.contains(|ch: char| !ch.is_ascii_alphanumeric() && ch != '_')
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{
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write!(f, "{name:?}")?;
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} else {
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f.write_str(name)?;
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}
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}
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Ok(())
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}
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}
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impl fmt::Debug for MemoryInterfacesBundleFieldPath {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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fmt::Display::fmt(self, f)
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}
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
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pub struct MemoryInterfacesBundleField<
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T: ValueType<Type = MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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> {
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pub path: MemoryInterfacesBundleFieldPath,
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pub value: T,
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}
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#[derive(Clone, Debug)]
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pub struct MemoryInterfacesBundleProperties<
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T: ValueType<Type = MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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> {
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first_full_interface: Option<usize>,
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fields: Vec<MemoryInterfacesBundleField<T>>,
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}
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impl<T: ValueType<Type = MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>>
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MemoryInterfacesBundleProperties<T>
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{
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pub fn first_full_interface(&self) -> Option<usize> {
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self.first_full_interface
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}
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pub fn fields(&self) -> &[MemoryInterfacesBundleField<T>] {
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&self.fields
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}
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pub fn into_fields(self) -> Vec<MemoryInterfacesBundleField<T>> {
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self.fields
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}
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#[track_caller]
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pub fn from_fields(fields: Vec<MemoryInterfacesBundleField<T>>) -> Self {
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let mut first_full_interface = None;
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for (index, field) in fields.iter().enumerate() {
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let ty = field.value.ty();
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assert_eq!(
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ty, MemoryInterface[ty.config],
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"inconsistent field type: {}",
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field.path,
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);
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if let None = first_full_interface
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&& let AddressRange::Full = ty.config.get().address_range
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{
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first_full_interface = Some(index);
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}
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}
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Self {
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first_full_interface,
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fields,
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}
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}
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#[track_caller]
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fn get_fields<
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B: ValueType<Type = Bundle, ValueCategory = T::ValueCategory>,
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C: ValueType<Type = CanonicalType, ValueCategory = T::ValueCategory>,
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>(
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fields: &mut Vec<MemoryInterfacesBundleField<T>>,
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path_prefix: &mut Vec<Interned<str>>,
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bundle: B,
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get_field: impl Copy + Fn(&B, Interned<str>) -> C,
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interface_from_bundle: impl Copy + Fn(B) -> T,
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bundle_from_canonical: impl Copy + Fn(C) -> B,
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) {
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let bundle_fields = bundle.ty().fields();
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if bundle_fields.iter().any(|f| f.flipped)
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&& bundle_fields.iter().any(|f| *f.name == *"config")
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{
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let value = interface_from_bundle(bundle);
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fields.push(MemoryInterfacesBundleField {
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path: MemoryInterfacesBundleFieldPath::from_slice(path_prefix),
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value,
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});
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} else {
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for f in &bundle_fields {
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assert!(
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!f.flipped,
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"field must not have #[hdl(flip)]: {}",
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MemoryInterfacesBundleFieldPath::from_slice(path_prefix),
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);
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let field = get_field(&bundle, f.name);
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match field.ty() {
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CanonicalType::Bundle(_) => {
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path_prefix.push(f.name);
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Self::get_fields(
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fields,
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path_prefix,
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bundle_from_canonical(field),
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get_field,
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interface_from_bundle,
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bundle_from_canonical,
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);
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path_prefix.pop();
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}
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CanonicalType::PhantomConst(_) => continue,
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_ => panic!(
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"field type must be either a MemoryInterfacesBundle or a PhantomConst: {}",
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MemoryInterfacesBundleFieldPath::from_slice(path_prefix),
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),
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}
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}
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}
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}
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}
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/// `Self` is a bundle where either:
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/// * `Self` is a [`MemoryInterface<PhantomConst<MemoryInterfaceConfig>>`]
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/// * each field is a [`MemoryInterfacesBundle`] or a [`PhantomConst`] and none of the fields have `#[hdl(flip)]`
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pub trait MemoryInterfacesBundle: BundleType {
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#[track_caller]
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fn properties_valueless(
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self,
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mut path_prefix: Vec<Interned<str>>,
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) -> MemoryInterfacesBundleProperties<
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Valueless<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
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> {
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let mut fields = Vec::new();
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MemoryInterfacesBundleProperties::get_fields(
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&mut fields,
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&mut path_prefix,
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Valueless::new(Bundle::new(self.fields())),
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|&bundle, name| {
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Valueless::new(
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bundle
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.ty()
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.field_by_name(name)
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.expect("field is known to exist")
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.ty,
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)
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},
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|bundle| Valueless::new(MemoryInterface::from_canonical(bundle.ty().canonical())),
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|canonical| Valueless::new(Bundle::from_canonical(canonical.ty())),
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);
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MemoryInterfacesBundleProperties::from_fields(fields)
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}
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#[track_caller]
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fn properties_expr(
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this: impl ToExpr<Type = Self>,
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mut path_prefix: Vec<Interned<str>>,
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) -> MemoryInterfacesBundleProperties<Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>>
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{
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let mut fields = Vec::new();
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MemoryInterfacesBundleProperties::get_fields(
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&mut fields,
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&mut path_prefix,
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Expr::as_bundle(this.to_expr()),
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|&bundle, name| Expr::field(bundle, &name),
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Expr::from_bundle,
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Expr::from_canonical,
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);
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MemoryInterfacesBundleProperties::from_fields(fields)
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}
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}
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fn memory_interface_resize_adaptor_input_config(
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output_config: PhantomConst<MemoryInterfaceConfig>,
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input_log2_bus_width_in_bytes: u8,
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max_input_queue_capacity: Option<NonZeroUsize>,
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) -> PhantomConst<MemoryInterfaceConfig> {
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let output_config = *output_config.get();
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let MemoryInterfaceConfig {
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log2_bus_width_in_bytes: _,
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queue_capacity: output_queue_capacity,
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op_id_width,
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address_range,
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} = output_config;
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let mut input_config = MemoryInterfaceConfig {
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log2_bus_width_in_bytes: input_log2_bus_width_in_bytes,
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queue_capacity: output_queue_capacity,
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op_id_width,
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address_range,
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};
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if let Some(ratio) =
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NonZeroUsize::new(input_config.bus_width_in_bytes() / output_config.bus_width_in_bytes())
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{
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input_config.queue_capacity = output_queue_capacity.div_ceil(ratio)
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}
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if let Some(max_input_queue_capacity) = max_input_queue_capacity
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&& max_input_queue_capacity < input_config.queue_capacity
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{
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input_config.queue_capacity = max_input_queue_capacity;
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}
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PhantomConst::new_sized(input_config)
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}
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#[hdl_module]
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fn memory_interface_resize_adaptor(
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input_config: PhantomConst<MemoryInterfaceConfig>,
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output_config: PhantomConst<MemoryInterfaceConfig>,
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) {
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let expected_input_config = memory_interface_resize_adaptor_input_config(
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output_config,
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input_config.get().log2_bus_width_in_bytes,
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Some(input_config.get().queue_capacity),
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);
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assert_eq!(input_config, expected_input_config);
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let input_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
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m.input(MemoryInterface[input_config]);
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#[hdl]
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let output_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
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m.output(MemoryInterface[output_config]);
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let log2_split_count = output_config
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.get()
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.log2_bus_width_in_bytes
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.saturating_sub(input_config.get().log2_bus_width_in_bytes);
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let split_count = 1usize.strict_shl(log2_split_count.into());
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let log2_split_count = usize::from(log2_split_count);
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connect(
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input_interface.next_op_ids,
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input_interface.ty().next_op_ids.HdlNone(),
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);
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#[hdl(no_static)]
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struct Entry<C: PhantomConstGet<MemoryInterfaceConfig>, SplitCount: Size> {
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addr: UInt<64>,
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active_split_chunks: ArrayType<Bool, SplitCount>,
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config: C,
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}
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#[hdl]
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let queue = instance(queue(
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Entry[input_config][split_count],
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input_config.get().queue_capacity,
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false,
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false,
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));
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connect(queue.cd, cd);
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#[hdl(no_static)]
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struct IncompleteStartState<C: PhantomConstGet<MemoryInterfaceConfig>, SplitCount: Size> {
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start: MemoryOperationStart<C>,
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active_split_chunks: ArrayType<Bool, SplitCount>,
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split_chunks_left: ArrayType<Bool, SplitCount>,
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}
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#[hdl]
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let incomplete_start_state_reg = reg_builder()
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.clock_domain(cd)
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.reset(HdlOption[IncompleteStartState[input_config][split_count]].HdlNone());
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connect(input_interface.start.ready, queue.inp.ready);
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connect(
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output_interface.start.data,
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output_interface.ty().start.data.HdlNone(),
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);
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#[hdl]
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let prev_incomplete_start_state = wire(incomplete_start_state_reg.ty());
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#[hdl]
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if let HdlSome(start) = input_interface.start.data {
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#[hdl]
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let start_active_split_chunks = wire(Array[Bool][split_count]);
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#[hdl]
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if start.rw_mask.cast_to_bits().all_zero_bits() {
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// if rw_mask is all false, set start_active_split_chunks to [true, false, false, false, ...] so we make at least one transaction on output_interface
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connect(start_active_split_chunks, repeat(false, split_count));
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connect(start_active_split_chunks[0], true);
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} else {
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// otherwise, split rw_mask into chunks of size at most output_config.get().bus_width_in_bytes()
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for (split_chunk, rw_mask_chunk) in start_active_split_chunks.into_iter().zip(
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start
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.rw_mask
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.chunks(output_config.get().bus_width_in_bytes()),
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) {
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connect(split_chunk, rw_mask_chunk.cast_to_bits().any_one_bits());
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}
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}
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connect(
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prev_incomplete_start_state,
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HdlSome(
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#[hdl]
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IncompleteStartState::<_, _> {
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start,
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active_split_chunks: start_active_split_chunks,
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split_chunks_left: start_active_split_chunks,
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},
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),
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);
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} else {
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connect(
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prev_incomplete_start_state,
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prev_incomplete_start_state.ty().HdlNone(),
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);
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}
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#[hdl]
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if let HdlSome(_) = incomplete_start_state_reg {
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connect(input_interface.start.ready, false);
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connect(prev_incomplete_start_state, incomplete_start_state_reg);
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}
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connect(
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incomplete_start_state_reg,
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incomplete_start_state_reg.ty().HdlNone(),
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);
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#[hdl]
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if let HdlSome(incomplete_start_state) = prev_incomplete_start_state {
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#[hdl]
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let IncompleteStartState::<_, _> {
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start,
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active_split_chunks,
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split_chunks_left,
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} = incomplete_start_state;
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// we know at least one element of split_chunks_left is true
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#[hdl]
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let start_split_chunk_selected = wire(UInt[log2_split_count]);
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// use last-connect semantics to get the index of the first element of split_chunks_left that's true
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for (i, split_chunk_left) in split_chunks_left.into_iter().enumerate().rev() {
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if i == split_count - 1 {
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connect_any(start_split_chunk_selected, i);
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continue;
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}
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#[hdl]
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if split_chunk_left {
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connect_any(start_split_chunk_selected, i);
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}
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}
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let output_data_shift = todo!();
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connect(
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output_interface.start.data,
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HdlSome(
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#[hdl]
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MemoryOperationStart::<_> {
|
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kind: start.kind,
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addr: start.addr
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+ start_split_chunk_selected * todo!("chunk size")
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+ todo!("mask addr"),
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write_data,
|
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rw_mask,
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op_id,
|
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config,
|
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},
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),
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);
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}
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#[hdl(no_static)]
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struct IncompleteFinishState<C: PhantomConstGet<MemoryInterfaceConfig>, SplitCount: Size> {
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addr: UInt<64>,
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finish: MemoryOperationFinish<C>,
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split_chunks_left: ArrayType<Bool, SplitCount>,
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}
|
||||
|
||||
#[hdl]
|
||||
let incomplete_finish_state_reg = reg_builder()
|
||||
.clock_domain(cd)
|
||||
.reset(HdlOption[IncompleteFinishState[input_config][split_count]].HdlNone());
|
||||
|
||||
todo!();
|
||||
}
|
||||
|
||||
#[hdl_module]
|
||||
pub fn memory_interface_adaptor<OutputInterfaces: Type + MemoryInterfacesBundle>(
|
||||
input_interface_config: PhantomConst<MemoryInterfaceConfig>,
|
||||
output_interfaces_ty: OutputInterfaces,
|
||||
) {
|
||||
#[hdl]
|
||||
let cd: ClockDomain = m.input();
|
||||
#[hdl]
|
||||
let input_interface: MemoryInterface<PhantomConst<MemoryInterfaceConfig>> =
|
||||
m.input(MemoryInterface[input_interface_config]);
|
||||
#[hdl]
|
||||
let output_interfaces: OutputInterfaces = m.output(output_interfaces_ty);
|
||||
let mut output_interfaces = MemoryInterfacesBundle::properties_expr(
|
||||
output_interfaces,
|
||||
vec!["output_interfaces".intern()],
|
||||
);
|
||||
if let Some(index) = output_interfaces.first_full_interface() {
|
||||
assert!(
|
||||
index == output_interfaces.fields().len() - 1,
|
||||
"all fields after {path} will never be used since {path} comes before and handles all addresses",
|
||||
path = output_interfaces.fields[index].path,
|
||||
);
|
||||
} else {
|
||||
#[hdl]
|
||||
let always_error = instance(memory_interface_always_error(PhantomConst::new_sized(
|
||||
memory_interface_always_error_config(*input_interface_config.get()),
|
||||
)));
|
||||
let mut fields = output_interfaces.into_fields();
|
||||
fields.push(MemoryInterfacesBundleField {
|
||||
path: MemoryInterfacesBundleFieldPath::from_slice(&[
|
||||
"always_error".intern(),
|
||||
"input_interface".intern(),
|
||||
]),
|
||||
value: always_error.input_interface,
|
||||
});
|
||||
output_interfaces = MemoryInterfacesBundleProperties::from_fields(fields);
|
||||
}
|
||||
|
||||
fn visit_selected_output_interface(
|
||||
output_interfaces: &MemoryInterfacesBundleProperties<
|
||||
Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>,
|
||||
>,
|
||||
selected_output_interface: impl ToExpr<Type = UIntInRangeType<ConstUsize<0>, DynSize>>,
|
||||
mut visit_selected: impl FnMut(
|
||||
usize,
|
||||
MemoryInterfacesBundleField<Expr<MemoryInterface<PhantomConst<MemoryInterfaceConfig>>>>,
|
||||
),
|
||||
) {
|
||||
let selected_output_interface = selected_output_interface.to_expr();
|
||||
let mut else_scope = None;
|
||||
for (i, &interface) in output_interfaces.fields().iter().enumerate() {
|
||||
if i == output_interfaces.fields().len() - 1 {
|
||||
// just else, no else if
|
||||
visit_selected(i, interface);
|
||||
} else {
|
||||
let if_scope = fayalite::module::if_(selected_output_interface.cmp_eq(i));
|
||||
visit_selected(i, interface);
|
||||
else_scope = Some(if_scope.else_());
|
||||
}
|
||||
}
|
||||
drop(else_scope);
|
||||
}
|
||||
|
||||
#[hdl(no_static)]
|
||||
struct Op<C: PhantomConstGet<MemoryInterfaceConfig>, OutputInterfaceCount: Size> {
|
||||
start: MemoryOperationStart<C>,
|
||||
output_interface_index: UIntInRangeType<ConstUsize<0>, OutputInterfaceCount>,
|
||||
started_bytes: UIntInRangeInclusiveType<ConstUsize<0>, MemoryInterfaceBusWidthInBytes<C>>,
|
||||
finished_bytes: UIntInRangeInclusiveType<ConstUsize<0>, MemoryInterfaceBusWidthInBytes<C>>,
|
||||
}
|
||||
|
||||
let op_ty = Op[input_interface_config][output_interfaces.fields().len()];
|
||||
let option_op_ty = HdlOption[op_ty];
|
||||
|
||||
#[hdl]
|
||||
let not_started_op_queue = instance(queue(
|
||||
op_ty,
|
||||
const { NonZeroUsize::new(2).unwrap() },
|
||||
false,
|
||||
true,
|
||||
));
|
||||
|
||||
connect(not_started_op_queue.cd, cd);
|
||||
connect(
|
||||
not_started_op_queue.inp.data,
|
||||
HdlOption::map(input_interface.start.data, |start| {
|
||||
#[hdl]
|
||||
let output_interface_index = wire(op_ty.output_interface_index);
|
||||
connect(
|
||||
output_interface_index,
|
||||
(output_interfaces.fields().len() - 1).cast_to(output_interface_index.ty()),
|
||||
);
|
||||
#[hdl]
|
||||
Op::<_, _> {
|
||||
start,
|
||||
output_interface_index,
|
||||
started_bytes: 0u8.cast_to(op_ty.started_bytes),
|
||||
finished_bytes: 0u8.cast_to(op_ty.finished_bytes),
|
||||
}
|
||||
}),
|
||||
);
|
||||
connect(input_interface.start.ready, not_started_op_queue.inp.ready);
|
||||
|
||||
#[hdl]
|
||||
let starting_op_reg = reg_builder().clock_domain(cd).reset(option_op_ty.HdlNone());
|
||||
|
||||
#[hdl]
|
||||
let starting_op_in = wire(option_op_ty);
|
||||
|
||||
#[hdl]
|
||||
if let HdlSome(_) = starting_op_reg {
|
||||
connect(starting_op_in, starting_op_reg);
|
||||
connect(not_started_op_queue.out.ready, false);
|
||||
} else {
|
||||
connect(starting_op_in, not_started_op_queue.out.data);
|
||||
connect(not_started_op_queue.out.ready, true);
|
||||
}
|
||||
|
||||
for output_interface in output_interfaces.fields() {
|
||||
connect(
|
||||
output_interface.value.start.data,
|
||||
output_interface.value.ty().start.data.HdlNone(),
|
||||
);
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
if let HdlSome(starting_op_in) = starting_op_in {
|
||||
#[hdl]
|
||||
let Op::<_, _> {
|
||||
start,
|
||||
output_interface_index,
|
||||
started_bytes,
|
||||
finished_bytes,
|
||||
} = starting_op_in;
|
||||
#[hdl]
|
||||
let MemoryOperationStart::<_> {
|
||||
kind,
|
||||
addr,
|
||||
write_data,
|
||||
rw_mask,
|
||||
op_id,
|
||||
config,
|
||||
} = start;
|
||||
visit_selected_output_interface(
|
||||
&output_interfaces,
|
||||
output_interface_index,
|
||||
|_, output_interface| {
|
||||
connect(
|
||||
output_interface.value.start.data,
|
||||
#[hdl]
|
||||
MemoryOperationStart::<_> { kind },
|
||||
);
|
||||
#[hdl]
|
||||
if output_interface.value.start {
|
||||
todo();
|
||||
}
|
||||
todo!();
|
||||
},
|
||||
);
|
||||
} else {
|
||||
connect(starting_op_reg, option_op_ty.HdlNone());
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
let started_op_queue = instance(queue(
|
||||
op_ty,
|
||||
input_interface_config.get().queue_capacity,
|
||||
false,
|
||||
false,
|
||||
));
|
||||
|
||||
#[hdl]
|
||||
let finishing_op_reg = reg_builder().clock_domain(cd).reset(option_op_ty.HdlNone());
|
||||
|
||||
todo!()
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue