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change bit-vector AC simplification n to true
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@ -7,7 +7,7 @@ def_module_params(module_name='rewriter',
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("elim_sign_ext", BOOL, True, "expand sign-ext operator using concat and extract"),
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("hi_div0", BOOL, True, "use the 'hardware interpretation' for division by zero (for bit-vector terms)"),
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("mul2concat", BOOL, False, "replace multiplication by a power of two into a concatenation"),
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("bv_sort_ac", BOOL, False, "sort the arguments of all AC operators"),
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("bv_sort_ac", BOOL, True, "sort the arguments of all AC operators"),
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("bv_extract_prop", BOOL, False, "attempt to partially propagate extraction inwards"),
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("bv_not_simpl", BOOL, False, "apply simplifications for bvnot"),
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("bv_ite2id", BOOL, False, "rewrite ite that can be simplified to identity"),
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