yosys/tests/verilog/genfor_decl_no_sv.ys at ffe87fbb343d0925a65a12fde2be88a633306816 - mirrors/yosys - Libre-Chip.org

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Zachary Snow b2e9717419 sv: support declaration in generate for initialization

This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.

2021-08-31 12:34:55 -06:00

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 logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1
 read_verilog <<EOT
 module top;
     for (genvar i = 1; i < 10; i = i + 1)
         wire x;
 endmodule
 EOT