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f0a52e3dd2
In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
32 lines
480 B
Systemverilog
32 lines
480 B
Systemverilog
module gate(x);
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output reg [15:0] x;
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if (1) begin : gen
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integer x;
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initial begin
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for (integer x = 5; x < 10; x++)
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if (x == 5)
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gen.x = 0;
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else
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gen.x += 2 ** x;
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x = x * 2;
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end
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end
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initial x = gen.x;
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endmodule
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module gold(x);
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output reg [15:0] x;
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if (1) begin : gen
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integer x;
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integer z;
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initial begin
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for (z = 5; z < 10; z++)
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if (z == 5)
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x = 0;
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else
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x += 2 ** z;
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x = x * 2;
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end
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end
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initial x = gen.x;
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endmodule
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