mirror of
https://github.com/YosysHQ/yosys
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177 lines
4 KiB
Text
177 lines
4 KiB
Text
design -reset
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read_verilog <<EOT
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module test(input a, output [7:0] y);
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assign y = a * 0;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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# The multiplication by zero should be replaced with constant zero
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select -assert-count 0 t:$mul
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## opt.opt_expr.mul_shift
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design -reset
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read_verilog <<EOT
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module test(input [7:0] a, output [15:0] y, output [15:0] z);
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assign y = a * 8; // Multiply by 2^3 (power of 2)
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assign z = 8 * a;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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# The multiplication by 8 should be replaced with a shift by const
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select -assert-count 0 t:$mul
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# No shift operator cells should be present
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select -assert-count 0 t:$shl
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design -reset
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read_verilog <<EOT
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module test(input [7:0] a, output [7:0] y);
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assign y = a / 4; // Division by 2^2 (power of 2)
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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# The division by 4 should be replaced with a shift by const
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select -assert-count 0 t:$div
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design -reset
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read_verilog <<EOT
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module test(input [7:0] a, output [7:0] y);
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assign y = a / 0; // Division by zero should be replaced with x
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endmodule
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EOT
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opt_expr -fine
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# The division by zero should be removed
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select -assert-count 0 t:$div
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# No cells should be left as it's replaced with constant undef
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select -assert-none t:*
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design -reset
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read_verilog <<EOT
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module test(input s, output y);
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assign y = s ? 1'b1 : 1'b0; // This is equivalent to just 's'
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine -mux_bool
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design -load postopt
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# The mux should be removed completely
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select -assert-count 0 t:$mux
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# No additional cells needed - direct connection
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select -assert-none t:*
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design -reset
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read_verilog <<EOT
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module test(input s, output y);
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assign y = s ? 1'b0 : 1'b1; // This is equivalent to '!s'
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine -mux_bool
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design -load postopt
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# The mux should be converted to a not gate
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$not
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design -reset
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read_verilog <<EOT
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module test(input [3:0] a, input [3:0] b, output y);
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assign y = (a == b); // Test equality optimization
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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# Check for optimization of equality comparison
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select -assert-count 1 t:$eq
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# opt.opt_expr.eqneq.*
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design -reset
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read_verilog -noopt <<EOT
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module test(output y1, y2, y3, y4);
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// Compare two constants that are guaranteed to be different
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assign y1 = 2'b01 == 2'b10;
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assign y2 = 2'b01 != 2'b10;
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assign y3 = 2'b01 !== 2'b10;
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assign y4 = 2'b01 === 2'b10;
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endmodule
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EOT
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equiv_opt -assert opt_expr
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select -assert-count 1 t:$eq
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design -load postopt
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# The comparison of different constants should be replaced with constant 0
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select -assert-count 0 t:$eq
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# No other cells should be present (just the constant driver)
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select -assert-none t:*
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# opt.opt_expr.invert.double
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design -reset
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read_verilog -noopt <<EOT
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module test(input a, output y);
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// Double negation should be optimized away
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wire not_a;
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assign not_a = ~a;
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assign y = ~not_a;
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endmodule
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EOT
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equiv_opt -assert opt_expr
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select -assert-count 2 t:$not
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design -load postopt
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# Both NOT gates should be eliminated
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opt_clean -purge
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select -assert-count 0 t:$not
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# No other cells should be present
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select -assert-none t:*
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# opt.opt_expr.reduce_xnor_not
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design -reset
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read_verilog -noopt <<EOT
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module test(input a, output y);
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assign y = ~^a; // XNOR reduction of a single bit
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endmodule
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EOT
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equiv_opt -assert opt_expr -full
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design -load postopt
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select -assert-count 0 t:$reduce_xnor
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select -assert-count 1 t:$not
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## opt.opt_expr.mod_mask
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design -reset
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read_verilog -noopt <<EOT
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module test(input [7:0] a, output [7:0] y);
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assign y = a % 8; // Modulo by power of 2
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endmodule
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EOT
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select -assert-count 1 t:$mod
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equiv_opt -assert opt_expr -full
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design -load postopt
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select -assert-count 0 t:$mod
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select -assert-count 0 t:$and
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## opt.opt_expr.eqneq.empty (indirectly)
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design -reset
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read_verilog -noopt <<EOT
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module test(output [7:0] y1);
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assign y1 = 7'b1 == 7'b1;
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endmodule
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EOT
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select -assert-count 1 t:$eq
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equiv_opt -assert opt_expr -full
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design -load postopt
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select -assert-count 0 t:$eq
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