mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
361 lines
13 KiB
C++
361 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2019 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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struct ClkbufmapPass : public Pass {
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ClkbufmapPass() : Pass("clkbufmap", "insert clock buffers on clock networks") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clkbufmap [options] [selection]\n");
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log("\n");
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log("Inserts clock buffers between nets connected to clock inputs and their drivers.\n");
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log("\n");
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log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n");
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log("attribute will be considered for clock buffer insertion.\n");
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log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n");
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log("'none' or 'bufr' one would specify:\n");
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log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n");
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log("as the selection.\n");
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log("\n");
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log(" -buf <celltype> <portname_out>:<portname_in>\n");
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log(" Specifies the cell type to use for the clock buffers\n");
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log(" and its port names. The first port will be connected to\n");
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log(" the clock network sinks, and the second will be connected\n");
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log(" to the actual clock source.\n");
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log("\n");
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log(" -inpad <celltype> <portname_out>:<portname_in>\n");
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log(" If specified, a PAD cell of the given type is inserted on\n");
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log(" clock nets that are also top module's inputs (in addition\n");
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log(" to the clock buffer, if any).\n");
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log("\n");
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log("At least one of -buf or -inpad should be specified.\n");
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}
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void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
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if (modules_processed.count(module))
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return;
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for (auto cell : module->cells()) {
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Module *submodule = design->module(cell->type);
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if (!submodule)
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continue;
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module_queue(design, submodule, modules_sorted, modules_processed);
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}
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modules_sorted.push_back(module);
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modules_processed.insert(module);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing CLKBUFMAP pass (inserting clock buffers).\n");
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std::string buf_celltype, buf_portname, buf_portname2;
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-buf" && argidx+2 < args.size()) {
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buf_celltype = args[++argidx];
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buf_portname = args[++argidx];
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split_portname_pair(buf_portname, buf_portname2);
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continue;
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}
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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split_portname_pair(inpad_portname, inpad_portname2);
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continue;
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}
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break;
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}
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bool select = false;
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if (argidx < args.size()) {
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if (args[argidx].compare(0, 1, "-") != 0)
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select = true;
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extra_args(args, argidx, design);
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}
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if (buf_celltype.empty() && inpad_celltype.empty())
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log_error("Either the -buf option or -inpad option is required.\n");
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// Cell type, port name, bit index.
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pool<pair<IdString, pair<IdString, int>>> sink_ports;
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pool<pair<IdString, pair<IdString, int>>> buf_ports;
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
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// If true, use both ther -buf and -inpad cell for input ports that are clocks.
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bool buffer_inputs = true;
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Module *inpad_mod = design->module(RTLIL::escape_id(inpad_celltype));
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if (inpad_mod) {
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Wire *buf_wire = inpad_mod->wire(RTLIL::escape_id(buf_portname));
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if (buf_wire && buf_wire->get_bool_attribute(ID::clkbuf_driver))
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buffer_inputs = false;
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}
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// Process submodules before module using them.
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std::vector<Module *> modules_sorted;
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pool<Module *> modules_processed;
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for (auto module : design->selected_modules())
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module_queue(design, module, modules_sorted, modules_processed);
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for (auto module : modules_sorted)
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{
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if (module->get_blackbox_attribute()) {
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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if (wire->get_bool_attribute(ID::clkbuf_driver))
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for (int i = 0; i < GetSize(wire); i++)
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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if (wire->get_bool_attribute(ID::clkbuf_sink))
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for (int i = 0; i < GetSize(wire); i++)
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sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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auto it = wire->attributes.find(ID::clkbuf_inv);
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if (it != wire->attributes.end()) {
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IdString in_name = RTLIL::escape_id(it->second.decode_string());
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for (int i = 0; i < GetSize(wire); i++) {
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inv_ports_out[make_pair(module->name, make_pair(wire->name, i))] = make_pair(in_name, i);
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inv_ports_in[make_pair(module->name, make_pair(in_name, i))] = make_pair(wire->name, i);
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}
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}
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}
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continue;
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}
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pool<SigBit> sink_wire_bits;
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pool<SigBit> buf_wire_bits;
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pool<SigBit> driven_wire_bits;
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SigMap sigmap(module);
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// bit -> (buffer, buffer's input)
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dict<SigBit, pair<Cell *, Wire *>> buffered_bits;
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// First, collect nets that could use a clock buffer.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (int i = 0; i < port.second.size(); i++)
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if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
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sink_wire_bits.insert(sigmap(port.second[i]));
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// Second, collect ones that already have a clock buffer.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (int i = 0; i < port.second.size(); i++)
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if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
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buf_wire_bits.insert(sigmap(port.second[i]));
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// Third, propagate tags through inverters.
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bool retry = true;
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while (retry) {
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retry = false;
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (int i = 0; i < port.second.size(); i++) {
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auto it = inv_ports_out.find(make_pair(cell->type, make_pair(port.first, i)));
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auto bit = sigmap(port.second[i]);
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// If output of an inverter is connected to a sink, mark it as buffered,
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// and request a buffer on the inverter's input instead.
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if (it != inv_ports_out.end() && !buf_wire_bits.count(bit) && sink_wire_bits.count(bit)) {
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buf_wire_bits.insert(bit);
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auto other_bit = sigmap(cell->getPort(it->second.first)[it->second.second]);
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sink_wire_bits.insert(other_bit);
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retry = true;
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}
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// If input of an inverter is marked as already-buffered,
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// mark its output already-buffered as well.
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auto it2 = inv_ports_in.find(make_pair(cell->type, make_pair(port.first, i)));
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if (it2 != inv_ports_in.end() && buf_wire_bits.count(bit)) {
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auto other_bit = sigmap(cell->getPort(it2->second.first)[it2->second.second]);
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if (!buf_wire_bits.count(other_bit)) {
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buf_wire_bits.insert(other_bit);
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retry = true;
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}
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}
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}
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};
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// Collect all driven bits.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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if (cell->output(port.first))
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for (int i = 0; i < port.second.size(); i++)
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driven_wire_bits.insert(port.second[i]);
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// Insert buffers.
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std::vector<pair<Wire *, Wire *>> input_queue;
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// Copy current wire list, as we will be adding new ones during iteration.
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std::vector<Wire *> wires(module->wires());
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for (auto wire : wires)
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{
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// Should not happen.
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if (wire->port_input && wire->port_output)
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continue;
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bool process_wire = module->selected(wire);
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if (!select && wire->get_bool_attribute(ID::clkbuf_inhibit))
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process_wire = false;
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if (!process_wire) {
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// This wire is supposed to be bypassed, so make sure we don't buffer it in
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// some buffer higher up in the hierarchy.
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if (wire->port_output)
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for (int i = 0; i < GetSize(wire); i++)
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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continue;
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}
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pool<int> input_bits;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (buf_wire_bits.count(mapped_wire_bit)) {
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// Already buffered downstream. If this is an output, mark it.
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if (wire->port_output)
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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} else if (!sink_wire_bits.count(mapped_wire_bit)) {
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// Nothing to do.
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} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
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// Clock network not yet buffered, driven by one of
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// our cells or a top-level input -- buffer it.
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Wire *iwire = nullptr;
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RTLIL::Cell *cell = nullptr;
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bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
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if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
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log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
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cell = module->addCell(NEWER_ID, RTLIL::escape_id(buf_celltype));
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iwire = module->addWire(NEWER_ID);
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cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
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cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
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}
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if (is_input) {
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log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
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RTLIL::Cell *cell2 = module->addCell(NEWER_ID, RTLIL::escape_id(inpad_celltype));
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if (iwire) {
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cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
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} else {
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cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
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cell = cell2;
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}
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iwire = module->addWire(NEWER_ID);
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cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
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}
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if (iwire)
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buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
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if (wire->port_input) {
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input_bits.insert(i);
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}
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} else if (wire->port_input) {
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// A clock input in a submodule -- mark it, let higher level
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// worry about it.
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if (wire->port_input)
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sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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}
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}
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if (!input_bits.empty()) {
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// This is an input port and some buffers were inserted -- we need
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// to create a new input wire and transfer attributes.
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Wire *new_wire = module->addWire(NEWER_ID, wire);
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for (int i = 0; i < wire->width; i++) {
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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auto it = buffered_bits.find(mapped_wire_bit);
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if (it != buffered_bits.end()) {
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module->connect(it->second.second, SigSpec(new_wire, i));
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} else {
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module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
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}
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}
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input_queue.push_back(make_pair(wire, new_wire));
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}
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}
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// Mark any newly-buffered output ports as such.
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for (auto wire : module->selected_wires()) {
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if (wire->port_input || !wire->port_output)
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continue;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (buffered_bits.count(mapped_wire_bit))
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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}
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}
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// Reconnect the drivers to buffer inputs.
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for (auto cell : module->cells())
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for (auto port : cell->connections()) {
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if (!cell->output(port.first))
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continue;
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig) {
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const auto it = buffered_bits.find(sigmap(bit));
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if (it == buffered_bits.end())
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continue;
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// Avoid substituting buffer's own output pin.
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if (cell == it->second.first)
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continue;
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bit = it->second.second;
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newsig = true;
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}
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if (newsig)
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cell->setPort(port.first, sig);
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}
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// This has to be done last, to avoid upsetting sigmap before the port reconnections.
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for (auto &it : input_queue) {
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Wire *wire = it.first;
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Wire *new_wire = it.second;
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module->swap_names(new_wire, wire);
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wire->attributes.clear();
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wire->port_id = 0;
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wire->port_input = false;
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wire->port_output = false;
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}
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module->fixup_ports();
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}
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}
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} ClkbufmapPass;
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PRIVATE_NAMESPACE_END
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