mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
ff9713dd86
Such ports cannot actually be created or used yet, this just adds the necessary plumbing in the helper. Subsequent commits will gradually add wide port support to various yosys passes.
547 lines
17 KiB
C++
547 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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void Mem::remove() {
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if (cell) {
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module->remove(cell);
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cell = nullptr;
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}
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if (mem) {
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module->memories.erase(mem->name);
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delete mem;
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mem = nullptr;
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}
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for (auto &port : rd_ports) {
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if (port.cell) {
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module->remove(port.cell);
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port.cell = nullptr;
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}
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}
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for (auto &port : wr_ports) {
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if (port.cell) {
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module->remove(port.cell);
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port.cell = nullptr;
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}
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}
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for (auto &init : inits) {
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if (init.cell) {
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module->remove(init.cell);
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init.cell = nullptr;
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}
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}
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}
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void Mem::emit() {
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check();
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std::vector<int> rd_left;
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for (int i = 0; i < GetSize(rd_ports); i++) {
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auto &port = rd_ports[i];
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if (port.removed) {
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if (port.cell) {
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module->remove(port.cell);
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}
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} else {
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rd_left.push_back(i);
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}
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}
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std::vector<int> wr_left;
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for (int i = 0; i < GetSize(wr_ports); i++) {
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auto &port = wr_ports[i];
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if (port.removed) {
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if (port.cell) {
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module->remove(port.cell);
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}
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} else {
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wr_left.push_back(i);
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}
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}
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for (int i = 0; i < GetSize(rd_left); i++)
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if (i != rd_left[i])
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std::swap(rd_ports[i], rd_ports[rd_left[i]]);
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rd_ports.resize(GetSize(rd_left));
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for (int i = 0; i < GetSize(wr_left); i++)
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if (i != wr_left[i])
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std::swap(wr_ports[i], wr_ports[wr_left[i]]);
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wr_ports.resize(GetSize(wr_left));
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// for future: handle transparency mask here
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for (auto &port : wr_ports) {
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for (int i = 0; i < GetSize(wr_left); i++)
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port.priority_mask[i] = port.priority_mask[wr_left[i]];
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port.priority_mask.resize(GetSize(wr_left));
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}
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if (packed) {
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if (mem) {
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module->memories.erase(mem->name);
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delete mem;
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mem = nullptr;
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}
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if (!cell) {
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if (memid.empty())
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memid = NEW_ID;
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cell = module->addCell(memid, ID($mem));
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}
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cell->attributes = attributes;
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cell->parameters[ID::MEMID] = Const(memid.str());
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cell->parameters[ID::WIDTH] = Const(width);
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cell->parameters[ID::OFFSET] = Const(start_offset);
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cell->parameters[ID::SIZE] = Const(size);
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cell->parameters[ID::RD_PORTS] = Const(GetSize(rd_ports));
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cell->parameters[ID::WR_PORTS] = Const(GetSize(wr_ports));
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Const rd_clk_enable, rd_clk_polarity, rd_transparent;
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Const wr_clk_enable, wr_clk_polarity;
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SigSpec rd_clk, rd_en, rd_addr, rd_data;
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SigSpec wr_clk, wr_en, wr_addr, wr_data;
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int abits = 0;
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for (auto &port : rd_ports)
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abits = std::max(abits, GetSize(port.addr));
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for (auto &port : wr_ports)
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abits = std::max(abits, GetSize(port.addr));
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cell->parameters[ID::ABITS] = Const(abits);
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for (auto &port : rd_ports) {
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// TODO: remove
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log_assert(port.wide_log2 == 0);
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if (port.cell) {
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module->remove(port.cell);
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port.cell = nullptr;
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}
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rd_clk_enable.bits.push_back(State(port.clk_enable));
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rd_clk_polarity.bits.push_back(State(port.clk_polarity));
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rd_transparent.bits.push_back(State(port.transparent));
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rd_clk.append(port.clk);
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log_assert(GetSize(port.clk) == 1);
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rd_en.append(port.en);
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log_assert(GetSize(port.en) == 1);
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SigSpec addr = port.addr;
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addr.extend_u0(abits, false);
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rd_addr.append(addr);
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log_assert(GetSize(addr) == abits);
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rd_data.append(port.data);
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log_assert(GetSize(port.data) == width);
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}
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if (rd_ports.empty()) {
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rd_clk_enable = State::S0;
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rd_clk_polarity = State::S0;
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rd_transparent = State::S0;
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}
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cell->parameters[ID::RD_CLK_ENABLE] = rd_clk_enable;
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cell->parameters[ID::RD_CLK_POLARITY] = rd_clk_polarity;
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cell->parameters[ID::RD_TRANSPARENT] = rd_transparent;
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cell->setPort(ID::RD_CLK, rd_clk);
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cell->setPort(ID::RD_EN, rd_en);
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cell->setPort(ID::RD_ADDR, rd_addr);
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cell->setPort(ID::RD_DATA, rd_data);
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for (auto &port : wr_ports) {
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// TODO: remove
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log_assert(port.wide_log2 == 0);
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if (port.cell) {
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module->remove(port.cell);
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port.cell = nullptr;
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}
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wr_clk_enable.bits.push_back(State(port.clk_enable));
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wr_clk_polarity.bits.push_back(State(port.clk_polarity));
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wr_clk.append(port.clk);
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log_assert(GetSize(port.clk) == 1);
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wr_en.append(port.en);
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log_assert(GetSize(port.en) == width);
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SigSpec addr = port.addr;
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addr.extend_u0(abits, false);
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wr_addr.append(addr);
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log_assert(GetSize(addr) == abits);
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wr_data.append(port.data);
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log_assert(GetSize(port.data) == width);
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}
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if (wr_ports.empty()) {
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wr_clk_enable = State::S0;
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wr_clk_polarity = State::S0;
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}
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cell->parameters[ID::WR_CLK_ENABLE] = wr_clk_enable;
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cell->parameters[ID::WR_CLK_POLARITY] = wr_clk_polarity;
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cell->setPort(ID::WR_CLK, wr_clk);
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cell->setPort(ID::WR_EN, wr_en);
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cell->setPort(ID::WR_ADDR, wr_addr);
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cell->setPort(ID::WR_DATA, wr_data);
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for (auto &init : inits) {
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if (init.cell) {
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module->remove(init.cell);
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init.cell = nullptr;
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}
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}
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cell->parameters[ID::INIT] = get_init_data();
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} else {
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if (cell) {
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module->remove(cell);
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cell = nullptr;
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}
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if (!mem) {
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if (memid.empty())
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memid = NEW_ID;
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mem = new RTLIL::Memory;
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mem->name = memid;
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module->memories[memid] = mem;
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}
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mem->width = width;
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mem->start_offset = start_offset;
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mem->size = size;
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for (auto &port : rd_ports) {
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memrd));
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::CLK_ENABLE] = port.clk_enable;
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port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
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port.cell->parameters[ID::TRANSPARENT] = port.transparent;
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port.cell->setPort(ID::CLK, port.clk);
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port.cell->setPort(ID::EN, port.en);
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port.cell->setPort(ID::ADDR, port.addr);
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port.cell->setPort(ID::DATA, port.data);
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}
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int idx = 0;
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for (auto &port : wr_ports) {
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if (!port.cell)
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port.cell = module->addCell(NEW_ID, ID($memwr));
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port.cell->parameters[ID::MEMID] = memid.str();
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port.cell->parameters[ID::ABITS] = GetSize(port.addr);
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port.cell->parameters[ID::WIDTH] = width << port.wide_log2;
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port.cell->parameters[ID::CLK_ENABLE] = port.clk_enable;
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port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
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port.cell->parameters[ID::PRIORITY] = idx++;
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port.cell->setPort(ID::CLK, port.clk);
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port.cell->setPort(ID::EN, port.en);
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port.cell->setPort(ID::ADDR, port.addr);
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port.cell->setPort(ID::DATA, port.data);
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}
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idx = 0;
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for (auto &init : inits) {
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if (!init.cell)
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init.cell = module->addCell(NEW_ID, ID($meminit));
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init.cell->parameters[ID::MEMID] = memid.str();
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init.cell->parameters[ID::ABITS] = GetSize(init.addr);
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init.cell->parameters[ID::WIDTH] = width;
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init.cell->parameters[ID::WORDS] = GetSize(init.data) / width;
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init.cell->parameters[ID::PRIORITY] = idx++;
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init.cell->setPort(ID::ADDR, init.addr);
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init.cell->setPort(ID::DATA, init.data);
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}
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}
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}
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void Mem::clear_inits() {
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for (auto &init : inits)
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if (init.cell)
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module->remove(init.cell);
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inits.clear();
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}
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Const Mem::get_init_data() const {
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Const init_data(State::Sx, width * size);
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for (auto &init : inits) {
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int offset = (init.addr.as_int() - start_offset) * width;
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for (int i = 0; i < GetSize(init.data); i++)
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if (0 <= i+offset && i+offset < GetSize(init_data))
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init_data.bits[i+offset] = init.data.bits[i];
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}
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return init_data;
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}
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void Mem::check() {
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int max_wide_log2 = 0;
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for (auto &port : rd_ports) {
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if (port.removed)
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continue;
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log_assert(GetSize(port.clk) == 1);
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log_assert(GetSize(port.en) == 1);
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log_assert(GetSize(port.data) == (width << port.wide_log2));
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if (!port.clk_enable) {
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log_assert(!port.transparent);
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}
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for (int j = 0; j < port.wide_log2; j++) {
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log_assert(port.addr[j] == State::S0);
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}
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max_wide_log2 = std::max(max_wide_log2, port.wide_log2);
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}
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for (int i = 0; i < GetSize(wr_ports); i++) {
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auto &port = wr_ports[i];
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if (port.removed)
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continue;
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log_assert(GetSize(port.clk) == 1);
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log_assert(GetSize(port.en) == (width << port.wide_log2));
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log_assert(GetSize(port.data) == (width << port.wide_log2));
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for (int j = 0; j < port.wide_log2; j++) {
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log_assert(port.addr[j] == State::S0);
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}
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max_wide_log2 = std::max(max_wide_log2, port.wide_log2);
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log_assert(GetSize(port.priority_mask) == GetSize(wr_ports));
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for (int j = 0; j < GetSize(wr_ports); j++) {
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auto &wport = wr_ports[j];
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if (port.priority_mask[j] && !wport.removed) {
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log_assert(j < i);
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log_assert(port.clk_enable == wport.clk_enable);
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if (port.clk_enable) {
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log_assert(port.clk == wport.clk);
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log_assert(port.clk_polarity == wport.clk_polarity);
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}
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}
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}
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}
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int mask = (1 << max_wide_log2) - 1;
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log_assert(!(start_offset & mask));
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log_assert(!(size & mask));
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}
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namespace {
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struct MemIndex {
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dict<IdString, pool<Cell *>> rd_ports;
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dict<IdString, pool<Cell *>> wr_ports;
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dict<IdString, pool<Cell *>> inits;
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MemIndex (Module *module) {
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for (auto cell: module->cells()) {
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if (cell->type == ID($memwr))
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wr_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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else if (cell->type == ID($memrd))
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rd_ports[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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else if (cell->type == ID($meminit))
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inits[cell->parameters.at(ID::MEMID).decode_string()].insert(cell);
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}
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}
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};
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Mem mem_from_memory(Module *module, RTLIL::Memory *mem, const MemIndex &index) {
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Mem res(module, mem->name, mem->width, mem->start_offset, mem->size);
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res.packed = false;
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res.mem = mem;
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res.attributes = mem->attributes;
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if (index.rd_ports.count(mem->name)) {
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for (auto cell : index.rd_ports.at(mem->name)) {
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MemRd mrd;
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mrd.cell = cell;
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mrd.attributes = cell->attributes;
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mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
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mrd.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
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mrd.transparent = cell->parameters.at(ID::TRANSPARENT).as_bool();
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mrd.clk = cell->getPort(ID::CLK);
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mrd.en = cell->getPort(ID::EN);
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mrd.addr = cell->getPort(ID::ADDR);
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mrd.data = cell->getPort(ID::DATA);
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mrd.wide_log2 = ceil_log2(GetSize(mrd.data) / mem->width);
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res.rd_ports.push_back(mrd);
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}
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}
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if (index.wr_ports.count(mem->name)) {
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std::vector<std::pair<int, MemWr>> ports;
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for (auto cell : index.wr_ports.at(mem->name)) {
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MemWr mwr;
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mwr.cell = cell;
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mwr.attributes = cell->attributes;
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mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
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mwr.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
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mwr.clk = cell->getPort(ID::CLK);
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mwr.en = cell->getPort(ID::EN);
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mwr.addr = cell->getPort(ID::ADDR);
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mwr.data = cell->getPort(ID::DATA);
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mwr.wide_log2 = ceil_log2(GetSize(mwr.data) / mem->width);
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ports.push_back(std::make_pair(cell->parameters.at(ID::PRIORITY).as_int(), mwr));
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}
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std::sort(ports.begin(), ports.end(), [](const std::pair<int, MemWr> &a, const std::pair<int, MemWr> &b) { return a.first < b.first; });
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for (auto &it : ports)
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res.wr_ports.push_back(it.second);
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}
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if (index.inits.count(mem->name)) {
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std::vector<std::pair<int, MemInit>> inits;
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for (auto cell : index.inits.at(mem->name)) {
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MemInit init;
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init.cell = cell;
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init.attributes = cell->attributes;
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auto addr = cell->getPort(ID::ADDR);
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auto data = cell->getPort(ID::DATA);
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if (!addr.is_fully_const())
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log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
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if (!data.is_fully_const())
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log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), log_id(cell));
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init.addr = addr.as_const();
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init.data = data.as_const();
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inits.push_back(std::make_pair(cell->parameters.at(ID::PRIORITY).as_int(), init));
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}
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std::sort(inits.begin(), inits.end(), [](const std::pair<int, MemInit> &a, const std::pair<int, MemInit> &b) { return a.first < b.first; });
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for (auto &it : inits)
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res.inits.push_back(it.second);
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}
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for (int i = 0; i < GetSize(res.wr_ports); i++) {
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auto &port = res.wr_ports[i];
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port.priority_mask.resize(GetSize(res.wr_ports));
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for (int j = 0; j < i; j++) {
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auto &oport = res.wr_ports[j];
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if (port.clk_enable != oport.clk_enable)
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continue;
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if (port.clk_enable && port.clk != oport.clk)
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continue;
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if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
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continue;
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port.priority_mask[j] = true;
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}
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}
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res.check();
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return res;
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}
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Mem mem_from_cell(Cell *cell) {
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Mem res(cell->module, cell->parameters.at(ID::MEMID).decode_string(),
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cell->parameters.at(ID::WIDTH).as_int(),
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cell->parameters.at(ID::OFFSET).as_int(),
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cell->parameters.at(ID::SIZE).as_int()
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);
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int abits = cell->parameters.at(ID::ABITS).as_int();
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res.packed = true;
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res.cell = cell;
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res.attributes = cell->attributes;
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Const &init = cell->parameters.at(ID::INIT);
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if (!init.is_fully_undef()) {
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int pos = 0;
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while (pos < res.size) {
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Const word = init.extract(pos * res.width, res.width, State::Sx);
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if (word.is_fully_undef()) {
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pos++;
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} else {
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int epos;
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for (epos = pos; epos < res.size; epos++) {
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Const eword = init.extract(epos * res.width, res.width, State::Sx);
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if (eword.is_fully_undef())
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break;
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}
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MemInit minit;
|
|
minit.addr = res.start_offset + pos;
|
|
minit.data = init.extract(pos * res.width, (epos - pos) * res.width, State::Sx);
|
|
res.inits.push_back(minit);
|
|
pos = epos;
|
|
}
|
|
}
|
|
}
|
|
for (int i = 0; i < cell->parameters.at(ID::RD_PORTS).as_int(); i++) {
|
|
MemRd mrd;
|
|
mrd.wide_log2 = 0;
|
|
mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool();
|
|
mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool();
|
|
mrd.transparent = cell->parameters.at(ID::RD_TRANSPARENT).extract(i, 1).as_bool();
|
|
mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1);
|
|
mrd.en = cell->getPort(ID::RD_EN).extract(i, 1);
|
|
mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits);
|
|
mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, res.width);
|
|
res.rd_ports.push_back(mrd);
|
|
}
|
|
for (int i = 0; i < cell->parameters.at(ID::WR_PORTS).as_int(); i++) {
|
|
MemWr mwr;
|
|
mwr.wide_log2 = 0;
|
|
mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool();
|
|
mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool();
|
|
mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1);
|
|
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, res.width);
|
|
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
|
|
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, res.width);
|
|
res.wr_ports.push_back(mwr);
|
|
}
|
|
for (int i = 0; i < GetSize(res.wr_ports); i++) {
|
|
auto &port = res.wr_ports[i];
|
|
port.priority_mask.resize(GetSize(res.wr_ports));
|
|
for (int j = 0; j < i; j++) {
|
|
auto &oport = res.wr_ports[j];
|
|
if (port.clk_enable != oport.clk_enable)
|
|
continue;
|
|
if (port.clk_enable && port.clk != oport.clk)
|
|
continue;
|
|
if (port.clk_enable && port.clk_polarity != oport.clk_polarity)
|
|
continue;
|
|
port.priority_mask[j] = true;
|
|
}
|
|
}
|
|
res.check();
|
|
return res;
|
|
}
|
|
|
|
}
|
|
|
|
std::vector<Mem> Mem::get_all_memories(Module *module) {
|
|
std::vector<Mem> res;
|
|
MemIndex index(module);
|
|
for (auto it: module->memories) {
|
|
res.push_back(mem_from_memory(module, it.second, index));
|
|
}
|
|
for (auto cell: module->cells()) {
|
|
if (cell->type == ID($mem))
|
|
res.push_back(mem_from_cell(cell));
|
|
}
|
|
return res;
|
|
}
|
|
|
|
std::vector<Mem> Mem::get_selected_memories(Module *module) {
|
|
std::vector<Mem> res;
|
|
MemIndex index(module);
|
|
for (auto it: module->memories) {
|
|
if (module->design->selected(module, it.second))
|
|
res.push_back(mem_from_memory(module, it.second, index));
|
|
}
|
|
for (auto cell: module->selected_cells()) {
|
|
if (cell->type == ID($mem))
|
|
res.push_back(mem_from_cell(cell));
|
|
}
|
|
return res;
|
|
}
|
|
|
|
Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
|
|
MemRd &port = rd_ports[idx];
|
|
|
|
if (!port.clk_enable)
|
|
return nullptr;
|
|
|
|
Cell *c;
|
|
|
|
if (port.transparent)
|
|
{
|
|
SigSpec sig_q = module->addWire(stringf("%s$rdreg[%d]$q", memid.c_str(), idx), GetSize(port.addr));
|
|
SigSpec sig_d = port.addr;
|
|
port.addr = sig_q;
|
|
c = module->addDffe(stringf("%s$rdreg[%d]", memid.c_str(), idx), port.clk, port.en, sig_d, sig_q, port.clk_polarity, true);
|
|
}
|
|
else
|
|
{
|
|
SigSpec sig_d = module->addWire(stringf("%s$rdreg[%d]$d", memid.c_str(), idx), GetSize(port.data));
|
|
SigSpec sig_q = port.data;
|
|
port.data = sig_d;
|
|
c = module->addDffe(stringf("%s$rdreg[%d]", memid.c_str(), idx), port.clk, port.en, sig_d, sig_q, port.clk_polarity, true);
|
|
}
|
|
|
|
log("Extracted %s FF from read port %d of %s.%s: %s\n", port.transparent ? "addr" : "data",
|
|
idx, log_id(module), log_id(memid), log_id(c));
|
|
|
|
port.en = State::S1;
|
|
port.clk = State::S0;
|
|
port.clk_enable = false;
|
|
port.clk_polarity = true;
|
|
port.transparent = false;
|
|
|
|
return c;
|
|
}
|