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yosys/tests
2024-05-03 16:42:41 +02:00
..
aiger read_aiger: Fix incorrect read of binary Aiger without outputs 2024-04-29 14:06:58 +01:00
arch Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
asicworld
bind
blif
bram
cxxrtl cxxrtl: Fix sdivmod 2024-03-30 07:56:11 +00:00
errors
fmt
fsm
hana
liberty
lut
memfile
memlib Move parameters to module declaration 2024-04-08 12:44:37 +02:00
memories Move parameters to module declaration 2024-04-08 12:44:37 +02:00
opt tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
opt_share
proc
realmath
rpc
sat
select
share
sim
simple write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00
simple_abc9
smv
sva tests/sva: Skip sva tests that use SBY until SBY is compatible again 2024-03-05 14:37:33 +01:00
svinterfaces
svtypes
techmap cellmatch: Rename the special design to $cellmatch 2024-05-03 16:42:41 +02:00
tools
unit
various add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
verific
verilog write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00
vloghtb
xprop
gen-tests-makefile.sh