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yosys/tests/memories
2026-05-18 08:50:38 +02:00
..
.gitignore Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
amber23_sram_byte_en.v
firrtl_938.v
generate_mk.py Make better validation 2026-05-18 08:50:38 +02:00
implicit_en.v
issue00335.v Move parameters to module declaration 2024-04-08 12:44:37 +02:00
issue00710.v
no_implicit_en.v
nordports.ys rtlil: Adjust internal check for $mem_v2 cells 2024-11-08 15:18:43 +01:00
read_arst.v
read_two_mux.v
shared_ports.v
simple_sram_byte_en.v
trans_addr_enable.v
trans_sdp.v
trans_sp.v
validate.py Make better validation 2026-05-18 08:50:38 +02:00
wide_all.v
wide_read_async.v
wide_read_mixed.v
wide_read_sync.v
wide_read_trans.v
wide_thru_priority.v
wide_write.v