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yosys/techlibs
David Shah fe95807f16 [wip] DSP48E1 sim model improvements
Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 13:09:12 +01:00
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achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
common Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
gowin Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
intel Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx [wip] DSP48E1 sim model improvements 2019-08-07 13:09:12 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00