Eddie Hung 5ebdc0f8e0 Merge pull request #1638 from YosysHQ/eddie/fix1631 ... clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*		2020-02-05 19:31:18 +01:00
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.gitignore
asserts.v
asserts.ys
asserts_seq.v
asserts_seq.ys
clk2fflogic.ys	More rigorous test	2020-01-16 09:15:42 -08:00
counters-repeat.v	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
counters-repeat.ys	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
counters.v
counters.ys
expose_dff.v
expose_dff.ys
initval.v	Wire with init on FF part, 1'bx on non-FF part	2019-08-24 15:05:44 -07:00
initval.ys	Even more obvious testcase	2019-12-11 23:52:05 -08:00
run-test.sh
share.v
share.ys
sizebits.sv	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
sizebits.ys	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
splice.v
splice.ys