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23 lines
1 KiB
Text
23 lines
1 KiB
Text
# Test memory macro gets ignored due to -ignore_buses
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read_verilog -noblackbox <<EOF
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module RM_IHPSG13_1P_64x64_c2_bm_bist();
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endmodule
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EOF
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read_liberty -lib -ignore_buses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
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# Test memory macro doesn't get ignored without -ignore_buses
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# and check the area and capacitance attributes are populated
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design -reset
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read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
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select -assert-mod-count 1 =RM_IHPSG13_1P_64x64_c2_bm_bist =A:area=50489.1328 %i
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select -assert-any =*/i:A_BIST_EN =*/a:capacitance=0.00401111 %i
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# Test import of unit delay arcs
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design -reset
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read_liberty -wb -unit_delay -ignore_miss_func foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
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# A->Y arc on nand2_1 exists
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select -assert-any =sg13g2_nand2_1/i:A %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Y %co1:+$specify2[DST] %i
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# D->Q arc on sdfbbp_1 doesn't
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select -assert-none =sg13g2_sdfbbp_1/i:D %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Q %co1:+$specify2[DST] %i
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