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yosys/tests
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-11-16 10:59:54 +01:00
..
aiger
arch synth_gatemate: Update pass 2021-11-13 21:53:25 +01:00
asicworld
bind
blif
bram
errors
fsm
hana
liberty
lut
memfile
memories
opt
opt_share
proc
realmath
rpc
sat
select
share
simple verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
simple_abc9
smv
sva
svinterfaces
svtypes
techmap dfflegalize: Add tests for aldff lowering. 2021-10-27 14:14:01 +02:00
tools
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various Support parameters using struct as a wiretype (#3050) 2021-11-16 10:59:54 +01:00
verilog verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
vloghtb
gen-tests-makefile.sh