3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-22 04:03:45 +00:00
yosys/techlibs/ecp5
David Shah 777864d02e ecp5: Demote conflicting FF init values to a warning
Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 11:26:20 +00:00
..
.gitignore
arith_map.v ecp5: Increase threshold for ALU mapping 2019-01-21 12:33:47 +00:00
bram.txt
brams_connect.py
brams_init.py
brams_map.v
cells_bb.v ecp5: Add DDRDLLA 2019-02-19 19:34:37 +00:00
cells_map.v ecp5: Compatibility with Migen AsyncResetSynchronizer 2019-02-25 13:24:30 +00:00
cells_sim.v Fix ECP5 cells_sim for iverilog 2019-03-01 19:25:23 +01:00
dram.txt
drams_map.v
ecp5_ffinit.cc ecp5: Demote conflicting FF init values to a warning 2019-03-04 11:26:20 +00:00
latches_map.v ecp5: Add latch inference 2018-10-19 15:16:40 +01:00
Makefile.inc ecp5: Support for flipflop initialisation 2019-01-22 16:02:56 +00:00
synth_ecp5.cc Merge pull request #794 from daveshah1/ecp5improve 2019-02-28 14:46:56 -08:00