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fd2ac3ad8d
yosys
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frontends
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Akash Levy
9d3b7f7474
Merge branch 'YosysHQ:main' into main
2025-02-26 09:51:44 -08:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
ast/dpicall: Stop using variable length array
2025-02-24 17:32:30 +01:00
blif
Resolve reg naming to some extent
2024-12-17 12:11:39 -08:00
json
liberty
read_liberty: Directly set
abc9_box
on fitting cells
2024-12-09 15:43:41 +01:00
rpc
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
Cleanup
2025-02-14 08:48:27 -08:00
verilog
verilog_parser: silence yynerrs warning
2024-10-15 08:32:55 -04:00