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50 lines
1.3 KiB
Text
50 lines
1.3 KiB
Text
read_verilog << EOT
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module top(input a, b, output o);
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wire c, d, e;
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bb bb1 (.a (a), .b (b), .o (c));
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sub_mod sub_inst (.a (a), .b (b), .o (e));
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some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
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endmodule
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(* blackbox *)
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module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
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endmodule
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module sub_mod(input a, b, output o);
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bb bb2 (.a (a), .b (b), .o (o));
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endmodule
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module some_mod(input a, b, c, output o);
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assign o = a & (b | c);
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endmodule
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EOT
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hierarchy -top top
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design -stash hier
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# removing cell
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design -load hier
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logger -expect log "Removing cell .*, making all cell outputs cutpoints" 1
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cutpoint sub_mod/bb2
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logger -check-expected
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logger -werror "Removing cell .*, making all cell outputs cutpoints"
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# removing wires
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design -load hier
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logger -expect log "Making wire .* a cutpoint" 1
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cutpoint top/c
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logger -check-expected
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logger -werror "Making wire .* a cutpoint"
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# removing output wires
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design -load hier
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logger -expect log "Making output wire .* a cutpoint" 1
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cutpoint sub_mod/o
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logger -check-expected
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logger -werror "Making output wire .* a cutpoint"
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# whole module optimization, doesn't do any of the previous
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design -load hier
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logger -expect log "Making all outputs of module .* cut points, removing module contents" 1
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cutpoint sub_mod
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logger -check-expected
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