David Shah 49b670ca38 sv: Add tests for SV always types ... Signed-off-by: David Shah <dave@ds0.me>		2019-11-21 21:06:28 +00:00
..
.gitignore	Speed up "make test" and related cleanups	2019-08-17 14:37:07 +02:00
abc9.v	Make abc9 test a bit more interesting	2019-08-30 20:31:53 -07:00
abc9.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
bug1462.ys	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
bug1480.ys	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
bug1496.ys	Fix #1496.	2019-11-18 04:16:48 +01:00
chparam.sh
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys	Add equiv_opt -multiclock	2019-09-11 13:55:59 +01:00
gzip_verilog.v.gz	Add support for reading gzip'd input files	2019-07-26 10:23:58 +01:00
gzip_verilog.ys	Add support for reading gzip'd input files	2019-07-26 10:23:58 +01:00
hierarchy.sh
hierarchy_defer.ys	Expand test with `hierarchy' without -auto-top	2019-09-03 12:17:26 -07:00
mem2reg.ys	Do not propagate mem2reg attribute through to result	2019-08-22 16:57:59 -07:00
muxcover.ys
muxpack.v
muxpack.ys	Removal of more stat calls from tests	2019-08-18 21:28:45 -07:00
peepopt.ys	Use sat -tempinduct and comments for why equiv_opt not sufficient	2019-10-03 11:11:50 -07:00
pmgen_reduce.ys	Add test for pmtest_test "reduce" demo pattern	2019-08-17 14:05:10 +02:00
pmux2shiftx.v
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh	Speed up "make test" and related cleanups	2019-08-17 14:37:07 +02:00
script.ys
shregmap.v
shregmap.ys	Remove Xilinx test	2019-08-22 16:18:07 -07:00
signext.ys
specify.v
specify.ys
submod_extract.ys
svalways.sh	sv: Add tests for SV always types	2019-11-21 21:06:28 +00:00
wreduce.ys	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
write_gzip.ys	Do not use Verific in tests/various/write_gzip.ys	2019-08-16 14:22:46 +02:00