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			9 lines
		
	
	
	
		
			109 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			9 lines
		
	
	
	
		
			109 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module top
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| (
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|     input [5:0] x,
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|     input [5:0] y,
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| 
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|     output [11:0] A,
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| );
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|     assign A =  x * y;
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| endmodule
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