3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-14 12:58:45 +00:00
yosys/tests/hana/test_simulation_sop_basic_8_test.v
2013-01-05 11:13:26 +01:00

4 lines
54 B
Verilog

module test(output out);
assign out = 1'b0;
endmodule