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https://github.com/YosysHQ/yosys
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52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
read_verilog adffs.v
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design -save read
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proc
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hierarchy -top adff
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDCE
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select -assert-none t:BUFG t:FDCE %% t:* %D
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design -load read
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proc
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hierarchy -top adffn
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:LUT1
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select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
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design -load read
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proc
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hierarchy -top dffs
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:LUT2
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select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
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design -load read
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proc
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hierarchy -top ndffnr
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDRE_1
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select -assert-count 1 t:LUT2
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select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
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