Clifford Wolf e9a756aa7a Merge pull request #1213 from YosysHQ/eddie/wreduce_add ... wreduce/opt_expr: improve width reduction for $add and $sub cells		2019-08-07 14:27:35 +02:00
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aiger	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
arch	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00
asicworld
bram
errors
fsm
hana
liberty
lut	Forgot to commit	2019-07-16 12:44:26 -07:00
memories	memory_dff: Fix checking of feedback mux input when more than one mux	2019-07-02 13:35:50 +01:00
opt	Refactor "opt_rmdff -sat"	2019-06-20 13:44:21 +02:00
realmath
sat
share
simple	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.	2019-07-31 09:27:38 -07:00
simple_abc9	Add tests/simple_abc9/.gitignore	2019-07-09 20:58:01 +02:00
smv
sva
svinterfaces
techmap
tools	autotest.sh to define _AUTOTB when test_autotb	2019-06-28 14:56:22 -07:00
unit
various	Add signed opt_expr tests	2019-08-06 15:40:30 -07:00
vloghtb