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https://github.com/YosysHQ/yosys
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37 lines
1.1 KiB
Text
37 lines
1.1 KiB
Text
read_verilog macc_simple_test.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
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extract -constports -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_test_01.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
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extract -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_test_02.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
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extract -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_xmap.v
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hierarchy -check -top macc_16_16_32;;
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show -prefix macc_simple_xmap -format pdf -notitle
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