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yosys/techlibs/common
2023-11-13 10:42:12 +01:00
..
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
mul2dsp.v
pmux2mux.v
prep.cc Run future as part of prep 2023-09-13 11:32:36 +02:00
simcells.v
simlib.v Support import of $future_ff 2023-09-13 11:32:36 +02:00
smtmap.v Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
synth.cc mult -> booth in synth.cc, to turn on use synth -booth 2023-09-08 16:44:59 -07:00
techmap.v Add bitwise $bweqx and $bwmux cells 2022-11-30 18:24:35 +01:00