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102 lines
3 KiB
Verilog
102 lines
3 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [19:0] a;
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wire [17:0] b;
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wire [37:0] z;
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assign a = (A_WIDTH == 20) ? A :
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(A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} :
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{{(20 - A_WIDTH){1'b0}}, A};
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assign b = (B_WIDTH == 18) ? B :
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(B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} :
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{{(18 - B_WIDTH){1'b0}}, B};
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(* is_inferred=1 *)
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dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
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.a_i (a),
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.b_i (b),
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.acc_fir_i (6'd0),
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.z_o (z),
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.feedback_i (3'd0),
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.load_acc_i (1'b0),
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.unsigned_a_i (!A_SIGNED),
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.unsigned_b_i (!B_SIGNED),
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.output_select_i (3'd0),
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.saturate_enable_i (1'b0),
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.shift_right_i (6'd0),
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.round_i (1'b0),
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.subtract_i (1'b0),
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.register_inputs_i (1'b0)
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);
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assign Y = z;
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endmodule
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module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [ 9:0] a;
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wire [ 8:0] b;
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wire [18:0] z;
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assign a = (A_WIDTH == 10) ? A :
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(A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} :
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{{(10 - A_WIDTH){1'b0}}, A};
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assign b = (B_WIDTH == 9) ? B :
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(B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} :
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{{( 9 - B_WIDTH){1'b0}}, B};
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(* is_inferred=1 *)
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dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
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.a_i (a),
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.b_i (b),
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.acc_fir_i (6'd0),
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.z_o (z),
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.feedback_i (3'd0),
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.load_acc_i (1'b0),
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.unsigned_a_i (!A_SIGNED),
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.unsigned_b_i (!B_SIGNED),
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.output_select_i (3'd0),
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.saturate_enable_i (1'b0),
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.shift_right_i (6'd0),
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.round_i (1'b0),
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.subtract_i (1'b0),
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.register_inputs_i (1'b0)
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);
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assign Y = z;
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endmodule
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