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31 lines
753 B
Verilog
31 lines
753 B
Verilog
module NX_GCK_U(SI1, SI2, CMD, SO);
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input CMD;
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input SI1;
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input SI2;
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output SO;
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parameter inv_in = 1'b0;
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parameter inv_out = 1'b0;
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parameter std_mode = "BYPASS";
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wire SI1_int = inv_in ? ~SI1 : SI1;
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wire SI2_int = inv_in ? ~SI2 : SI2;
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wire SO_int;
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generate if (std_mode == "BYPASS") begin
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assign SO_int = SI1_int;
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end
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else if (std_mode == "MUX") begin
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assign SO_int = CMD ? SI1_int : SI2_int;
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end
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else if (std_mode == "CKS") begin
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assign SO_int = CMD ? SI1_int : 1'b0;
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end
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else if (std_mode == "CSC") begin
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assign SO_int = CMD;
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end
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else
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$error("Unrecognised std_mode");
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endgenerate
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assign SO = inv_out ? ~SO_int : SO_int;
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endmodule
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