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yosys/techlibs/ice40
History
Marcelina Kościelnicka 1fc8c3a0d1 ice40: Use dfflegalize.
2020-07-05 05:12:09 +02:00
..
tests Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 2019-08-12 12:06:45 -07:00
.gitignore
abc9_model.v ice40: specify fixes 2020-02-27 10:17:29 -08:00
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt ice40: match memory inference attribute values case insensitive. 2020-02-06 14:58:20 +00:00
brams_init.py
brams_map.v
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
dsp_map.v
ff_map.v ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
ice40_braminit.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ice40_ffssr.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ice40_opt.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
latches_map.v
Makefile.inc ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
synth_ice40.cc ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00