mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
216 lines
6.7 KiB
C++
216 lines
6.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2023 N. Engelhardt <nak@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// ============================================================================
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struct QlBramMergeWorker {
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// can be used to record parameter values that have to match on both sides
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typedef dict<RTLIL::IdString, RTLIL::Const> MergeableGroupKeyType;
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RTLIL::Module *module;
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dict<MergeableGroupKeyType, pool<RTLIL::Cell*>> mergeable_groups;
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QlBramMergeWorker(RTLIL::Module* module) : module(module)
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{
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const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K);
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for (RTLIL::Cell* cell : module->selected_cells())
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{
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if(cell->type != split_cell_type) continue;
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if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
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if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue;
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mergeable_groups[get_key(cell)].insert(cell);
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}
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}
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static MergeableGroupKeyType get_key(RTLIL::Cell* cell)
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{
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MergeableGroupKeyType key;
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// For now, there are no restrictions on which cells can be merged
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(void) cell;
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return key;
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}
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const dict<RTLIL::IdString, RTLIL::IdString>& param_map(bool second)
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{
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static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
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{ ID(INIT), ID(INIT1) },
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{ ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) },
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{ ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) },
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{ ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) },
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{ ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) }
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};
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static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
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{ ID(INIT), ID(INIT2) },
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{ ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) },
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{ ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) },
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{ ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) },
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{ ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) }
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};
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if(second)
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return bram2_map;
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else
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return bram1_map;
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}
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const dict<RTLIL::IdString, RTLIL::IdString>& port_map(bool second)
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{
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static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
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{ ID(PORT_A_CLK), ID(PORT_A1_CLK) },
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{ ID(PORT_B_CLK), ID(PORT_B1_CLK) },
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{ ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) },
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{ ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) },
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{ ID(PORT_A_ADDR), ID(PORT_A1_ADDR) },
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{ ID(PORT_B_ADDR), ID(PORT_B1_ADDR) },
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{ ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) },
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{ ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) },
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{ ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) },
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{ ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) },
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{ ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) },
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{ ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) },
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{ ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) },
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{ ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) }
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};
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static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
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{ ID(PORT_A_CLK), ID(PORT_A2_CLK) },
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{ ID(PORT_B_CLK), ID(PORT_B2_CLK) },
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{ ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) },
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{ ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) },
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{ ID(PORT_A_ADDR), ID(PORT_A2_ADDR) },
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{ ID(PORT_B_ADDR), ID(PORT_B2_ADDR) },
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{ ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) },
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{ ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) },
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{ ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) },
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{ ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) },
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{ ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) },
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{ ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) },
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{ ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) },
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{ ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) }
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};
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if(second)
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return bram2_map;
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else
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return bram1_map;
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}
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void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
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{
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const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED);
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// Create the new cell
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RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type);
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log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name));
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for (auto &it : param_map(false))
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{
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if(bram1->hasParam(it.first))
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merged->setParam(it.second, bram1->getParam(it.first));
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}
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for (auto &it : param_map(true))
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{
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if(bram2->hasParam(it.first))
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merged->setParam(it.second, bram2->getParam(it.first));
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}
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for (auto &it : port_map(false))
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{
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if (bram1->hasPort(it.first))
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merged->setPort(it.second, bram1->getPort(it.first));
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else
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log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name));
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}
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for (auto &it : port_map(true))
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{
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if (bram2->hasPort(it.first))
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merged->setPort(it.second, bram2->getPort(it.first));
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else
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log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name));
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}
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merged->attributes = bram1->attributes;
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for (auto attr: bram2->attributes)
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if (!merged->has_attribute(attr.first))
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merged->attributes.insert(attr);
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// Remove the old cells
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module->remove(bram1);
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module->remove(bram2);
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}
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void merge_bram_groups()
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{
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for (auto &it : mergeable_groups)
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{
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while (it.second.size() > 1)
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{
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merge_brams(it.second.pop(), it.second.pop());
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}
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}
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}
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};
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struct QlBramMergePass : public Pass {
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QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ql_bram_merge [selection]\n");
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log("\n");
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log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n");
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log(" into a TDP36K cell operating in split mode\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing QL_BRAM_MERGE pass.\n");
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size_t argidx = 1;
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extra_args(args, argidx, design);
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for (RTLIL::Module* module : design->selected_modules())
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{
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QlBramMergeWorker worker(module);
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worker.merge_bram_groups();
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}
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}
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} QlBramMergePass;
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PRIVATE_NAMESPACE_END
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