Krystine Sherwin 57cd8d29db cellhelp: Add default format parse for simcells ... Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst. Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.		2024-10-15 07:16:40 +13:00
..
achronix
anlogic
common	cellhelp: Add default format parse for simcells	2024-10-15 07:16:40 +13:00
coolrunner2
easic
ecp5
efinix
fabulous
gatemate	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
gowin	Gowin. Add the EMCU primitive.	2024-09-11 10:18:51 +10:00
greenpak4	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
ice40
intel
intel_alm	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
lattice
microchip	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
nanoxplore	Cleanup of synth_nanoxplore pass	2024-09-03 10:15:50 +02:00
nexus
quicklogic	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
sf2
xilinx	Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json	2024-10-14 06:45:14 -07:00
.gitignore