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17 lines
218 B
Systemverilog
17 lines
218 B
Systemverilog
module unnamed_block_decl(z);
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output integer z;
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initial begin
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integer x;
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x = 1;
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begin
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integer y;
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y = x + 1;
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begin
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integer z;
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z = y + 1;
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y = z + 1;
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end
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z = y + 1;
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end
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end
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endmodule
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