mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-31 11:23:57 +00:00
9018d06a33
The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions. |
||
|---|---|---|
| .. | ||
| choices | ||
| .gitignore | ||
| abc9_map.v | ||
| abc9_model.v | ||
| abc9_unmap.v | ||
| adff2dff.v | ||
| cellhelp.py | ||
| cells.lib | ||
| cmp2lcu.v | ||
| cmp2lut.v | ||
| cmp2softlogic.v | ||
| dff2ff.v | ||
| gate2lut.v | ||
| gen_fine_ffs.py | ||
| Makefile.inc | ||
| mul2dsp.v | ||
| pmux2mux.v | ||
| prep.cc | ||
| simcells.v | ||
| simlib.v | ||
| smtmap.v | ||
| synth.cc | ||
| techmap.v | ||