Claire Wolf b597f85b13 Merge pull request #1718 from boqwxp/precise_locations ... Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.		2020-03-03 08:38:32 -08:00
..
bitpattern.h
calc.cc
cellaigs.cc	Use more ID::{A,B,Y,blackbox,whitebox}	2019-08-15 14:50:10 -07:00
cellaigs.h
celledges.cc	Use more ID::{A,B,Y,blackbox,whitebox}	2019-08-15 14:50:10 -07:00
celledges.h
celltypes.h	Use more ID::{A,B,Y,blackbox,whitebox}	2019-08-15 14:50:10 -07:00
consteval.h	Revert "SigSet<Cell*> to use stable compare class"	2019-09-13 09:49:15 -07:00
cost.h
driver.cc	Handle expect no warnings together with expected	2020-02-22 10:52:46 +01:00
hashlib.h
log.cc	Remove duplicate warning detection	2020-02-23 10:56:27 +01:00
log.h	Handle expect no warnings together with expected	2020-02-22 10:52:46 +01:00
macc.h	Use more ID::{A,B,Y,blackbox,whitebox}	2019-08-15 14:50:10 -07:00
modtools.h
register.cc	Add log_experimental() and experimental() API and "yosys -x"	2020-01-27 18:27:47 +01:00
register.h	Add log_experimental() and experimental() API and "yosys -x"	2020-01-27 18:27:47 +01:00
rtlil.cc	Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.	2020-02-23 07:22:26 +00:00
rtlil.h	Add and use SigSpec::reverse()	2020-01-28 10:37:16 -08:00
satgen.h	Use more ID::{A,B,Y,blackbox,whitebox}	2019-08-15 14:50:10 -07:00
sigtools.h	Spacing	2019-09-13 16:30:44 -07:00
timinginfo.h	Small fixes	2020-02-27 10:29:53 -08:00
utils.h
yosys.cc	Move abc9.* constpad entries to Abc9Pass::on_register()	2020-01-09 17:10:54 -08:00
yosys.h	log_dump() to support State enum	2019-10-02 17:49:07 -07:00