mirror of
https://github.com/YosysHQ/yosys
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550310e264
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
17 lines
939 B
Systemverilog
17 lines
939 B
Systemverilog
.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
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INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
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INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
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INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
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.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
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INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
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INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
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INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
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.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
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INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
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INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
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INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
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.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
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INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
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INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
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INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
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