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yosys/tests/arch
2020-05-25 10:09:05 -07:00
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anlogic
common
ecp5
efinix
gowin
ice40 test: ice40_dsp test to read +/ice40/cells_sim.v for default params 2020-04-22 16:35:35 -07:00
intel_alm intel_alm: direct LUTRAM cell instantiation 2020-05-07 21:03:13 +02:00
xilinx tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
run-test.sh