3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-08 10:25:19 +00:00
yosys/tests/arch
2020-02-24 02:41:08 +00:00
..
anlogic Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
common Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 2019-12-16 21:48:21 -08:00
ecp5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
efinix Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
gowin Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
ice40 Change attribute search value to specify precise location instead of simple line number. 2020-02-24 02:41:08 +00:00
xilinx xilinx: Add support for LUT RAM on LUT4-based devices. 2020-02-07 09:03:22 +01:00
run-test.sh Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00