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aiger
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arch
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ABC9: Cell Port Bug Patch (#3670)
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2023-04-22 16:24:36 -07:00 |
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asicworld
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bind
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blif
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Adding check for BLIF names command input plane size.
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2022-08-21 23:18:20 -05:00 |
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bram
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errors
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fsm
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tests: fsm to use a randomly-generated seed
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2020-04-24 14:31:33 -07:00 |
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hana
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liberty
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dfflibmap: Refactor to use dfflegalize internally.
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2020-07-09 18:51:03 +02:00 |
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lut
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Forgot to commit
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2019-07-16 12:44:26 -07:00 |
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memfile
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Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06 10:45:40 -03:00 |
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memlib
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More tests in memlib/generate.py
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2023-02-21 05:23:15 +13:00 |
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memories
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opt
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simplemap: Map $xnor to $_XNOR_ cells
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2022-11-29 19:06:45 +01:00 |
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opt_share
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proc
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realmath
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rpc
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sat
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select
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share
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sim
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Replace GNU specific invocation of basename(1) with the equivalent
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2022-10-23 11:02:18 +13:00 |
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simple
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verilog: Support module-scoped task/function calls
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2022-10-29 15:14:11 -04:00 |
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simple_abc9
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smv
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sva
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verific: Use new value change logic also for $stable of wide signals.
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2022-05-11 13:05:27 +02:00 |
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svinterfaces
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Resolve package types in interfaces (#3658)
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2023-02-12 18:25:39 -05:00 |
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svtypes
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Cleaner tests for RTLIL cells in struct_dynamic_range.sv
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2023-05-04 14:28:21 +02:00 |
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techmap
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add pmux option to bmuxmap for better fsm detection with verific frontend
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2023-01-30 16:12:53 +01:00 |
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tools
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support file locations containing spaces
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2022-08-08 20:30:50 +02:00 |
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unit
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various
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Merge pull request #3646 from YosysHQ/lofty/fix-3591
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2023-02-27 16:26:57 +01:00 |
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verific
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verific: Fix enum_values support and signed attribute values
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2023-03-15 09:51:36 +01:00 |
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verilog
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verilog: Fix const eval of unbased unsized constants
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2023-04-20 12:12:50 +02:00 |
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vloghtb
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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xprop
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xprop tests: Make iverilog invocation more portable
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2023-02-13 16:54:11 +01:00 |
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gen-tests-makefile.sh
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Out of bounds checking for struct/union members
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2023-02-19 23:25:08 +01:00 |
