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19 lines
413 B
Systemverilog
19 lines
413 B
Systemverilog
module top (input logic clock, ctrl);
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logic read, write, ready;
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demo uut (
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.clock(clock),
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.ctrl(ctrl)
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);
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assign read = uut.read;
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assign write = uut.write;
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assign ready = uut.ready;
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a_rw: assert property ( @(posedge clock) !(read && write) );
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`ifdef FAIL
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a_wr: assert property ( @(posedge clock) write |-> ready );
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`else
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a_wr: assert property ( @(posedge clock) write |=> ready );
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`endif
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endmodule
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