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yosys/backends
Catherine f6e36f0e54 cxxrtl: implement a generic record/replay interface.
This commit adds a reader/writer implementation for a file format
optimized for fast, single-pass storage and retrieval of design state
changes, as well as a recorder/replayer that integrate with the eval
and commit simulation steps to create replay logs and reproduce them
later.

This feature makes it possible to run a simulation once, recording
the stimulus as well as changes to the registers, and navigate to
a past time point in the simulation later without rerunning it.
Both the changes in inputs (stimulus) and changes in state are saved
so that navigation does not require calling `eval()` or `commit()`;
only a series of memory copy operations.

On a representative example of a SoC netlist, saving the replay log
while simulating it takes 150% of the time it would take to simulate
the same design without logging, which is a much lower overhead than
writing an equivalent full view (including memories) VCD waveform dump.
The replay log is also several times smaller than the VCD dump, and
more space savings are available as low hanging fruit.

Replaying the log has not been optimized and currently takes about
the same time as running the simulation in first place. However, it
is still useful since it provides fast navigation to an arbitrary time
point, something that rerunning the simulation does not allow for.

The current file format should be considered preliminary. It is not
very space-efficient, and my testing shows that a lot of time is spent
in the write() syscall in the kernel. Most likely, compression and/or
writing in another thread could improve performance by 10-20%. This
may be done at a later time.
2024-01-09 13:48:36 +00:00
..
aiger Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
blif Slightly adjust the wording of "write_blif" help 2023-07-10 12:41:43 +02:00
btor tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
cxxrtl cxxrtl: implement a generic record/replay interface. 2024-01-09 13:48:36 +00:00
edif Improve EDIF lib_cell_ports scan 2023-06-20 10:42:05 +02:00
firrtl tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
intersynth Intersynth URL 2021-06-09 12:42:52 +02:00
jny Drop stray 'cellaigs.h' include from backend passes 2023-07-10 12:45:03 +02:00
json Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
rtlil backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
simplec tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
smt2 Merge pull request #3887 from kivikakk/env-bash 2023-12-18 16:33:35 +01:00
smv tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
spice Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
table Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
verilog write_verilog: Handle edge case with non-pruned processes 2024-01-06 17:05:02 +01:00