mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 04:49:15 +00:00
147 lines
2.3 KiB
Text
147 lines
2.3 KiB
Text
read_verilog <<EOT
|
|
module add_1bit(
|
|
input a, b, c,
|
|
output [1:0] y
|
|
);
|
|
assign y = a + b + c;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 1 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_1bit_wide(
|
|
input a, b, c, d,
|
|
output [3:0] y
|
|
);
|
|
assign y = a + b + c + d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_wide_out(
|
|
input [7:0] a, b, c, d,
|
|
output [31:0] y
|
|
);
|
|
assign y = a + b + c + d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_mixed(
|
|
input [7:0] a,
|
|
input [3:0] b,
|
|
input [15:0] c,
|
|
input [7:0] d,
|
|
output [15:0] y
|
|
);
|
|
assign y = a + b + c + d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_signed(
|
|
input signed [7:0] a, b, c, d,
|
|
output signed [9:0] y
|
|
);
|
|
assign y = a + b + c + d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_repeated(
|
|
input [7:0] a,
|
|
output [7:0] y
|
|
);
|
|
assign y = a + a + a + a;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_const(
|
|
input [7:0] a, b, c,
|
|
output [7:0] y
|
|
);
|
|
assign y = a + b + c + 8'd42;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module add_two(
|
|
input [7:0] a, b, c, d, e, f, g, h,
|
|
output [7:0] y1, y2
|
|
);
|
|
assign y1 = a + b + c + d;
|
|
assign y2 = e + f + g + h;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 4 t:$fa
|
|
select -assert-count 2 t:$add
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module fir_4tap(
|
|
input clk,
|
|
input [15:0] x, c0, c1, c2, c3,
|
|
output reg [31:0] y
|
|
);
|
|
reg [15:0] x1, x2, x3;
|
|
always @(posedge clk) begin
|
|
x1 <= x;
|
|
x2 <= x1;
|
|
x3 <= x2;
|
|
end
|
|
|
|
wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
|
|
always @(posedge clk) y <= sum;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
csa_tree
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
design -reset
|